Abstract: The present invention provides a stacked chip scale package structure, wherein a lower chip and an upper chip are stacked on a substrate. Two rows of bonding pads are disposed on each of the upper and lower chips. The bonding pads on the upper and lower chips are parallel arranged. At least a dummy die is disposed below the suspended portion of the upper chip and at the side of the lower chip as a support during wire bonding. A gap is reserved between the dummy die and the lower chip. The present invention utilizes the design of dummy die to resolve the problem of die crack caused by wire bonding of suspended chip. Therefore, the present invention can flexibly adjust the size and installation direction of the upper chip to meet the requirement of substrate layout, and can also shorten the trace length on the substrate to enhance the electric performance thereof.

Abstract: The present invention provides a design structure of an plated wire of a fiducial mark for a die-dicing package. In the present structure, a cutting line is positioned between each two adjacent ball grid array (BGA) chips. There is configured a solder mask opening at the edge connecting region of the cutting lines. A fiducial mark is positioned in the opening of each BGA chip, wherein the fiducial mark is close to the cutting line and positioned a plated wire therein to pull from the fiducial mark to out the opening and to connect to the plated wire of the cutting line. So as all the plated wires utilizing the coverage of the solder mask can be entirely cut without the pulling problem from the cutter. The present invention provides a new design structure of the plated wire to overcome the burr effect of prior die dicing so as to enhance the product efficiency and decrease the manufacturing cost.