Abstract: A method is provided for reducing inter modulation distortion products using multi-carrier phase alignment of the type where a combined carrier signal is generated from the combined output carried waves of a plurality of numerically controlled oscillators in which the frequency of the carrier wave can be altered by changing an input value into the oscillator. In particular the initial phase of the output carrier waves is adjusted so that the peak amplitude of the combined carrier signal is minimized so that compression of the higher amplitude portions of the combined signal is reduced.

Abstract: Direct digital QAM modulation at an RF frequency is obtained from digitally synthesized RF signals which are generated for use as the two vectors. The two vectors are individually controlled in phase and summed to provide a combined phase and amplitude modulation that forms the modulated signal. The synthesized RF signal is generated from a higher reference frequency using a variable pulse stretching technique implemented with programmable delay lines. The amount of the pulse stretch in each cycle is controlled by a phase increment value. Pulse stretching can be extended beyond one cycle by pulse swallowing, allowing the generation of an RF signal from DC up to and including the input reference frequency. Phase modulation is added by digital control of the pulse stretching according to the phase modulation data bits.

Abstract: A method to improve the frequency resolution and phase noise of a synthesized RF signal results in superior instantaneous frequency change and phase modulation capability, wide frequency set ability, and suitability for implementation in a digital ASIC. The RF signal synthesis is achieved from a higher reference frequency clock signal using a variable pulse stretching technique. The amount of the pulse stretch in each cycle is set by a phase increment value and is implemented using programmable delay lines. Pulse stretching can be extended beyond one cycle by pulse swallowing, allowing the generation of an RF signal with frequencies from DC up to the input reference frequency. Phase modulation is incorporated by digital control of the phase stretching with the phase modulation bits.

Abstract: A system and method for data detection in a wireless communication system wherein the system comprises a receiver for receiving spatial-subspace data transmitted over a plurality of spatial-subspace channels of a sub-carrier which may comprise at least one of coded and uncoded spatial-subspace channels. The receiver comprises a receiver weighting unit for providing receive-weighed spatial-subspace data and a data estimation unit for performing an iterative processing method on the receive-weighted spatial-subspace data to estimate output data related to the input data symbol stream. The-iterative processing method comprises successively processing data on each of the plurality of spatial-subspace channels in the receive-weighted spatial-subspace data.

Abstract: A system and method for transmitting a plurality of input data symbol sub-streams over a plurality of spatial-subspace channels of a sub-carrier between a transmitter and the receiver. The plurality of input data symbol sub-streams are partitioned in a plurality of super-frames of data and weighted by a weight matrix derived from the singular value decomposition of a channel matrix corresponding to the sub-carrier by applying a partial SVD algorithm. The transmitter further inserts subspace training symbols into the plurality of input data symbol sub-streams and the receiver periodically processes the sub-space training symbols during each super-frame of the plurality of super-frames for estimating output data related to the input data symbol stream.

Abstract: A time-sliced discrete-time Phase Locked Loop which is suitable for simultaneously synchronizing multiple input signals to multiple output signals is provided by implementing a discrete-time phase detector, loop filter, and voltage controlled oscillator that together operate as a single discrete-time PLL in hardware and applying control logic to retrieve the history for each signal pair from a context memory (RAM), to enable the discrete-time PLL hardware, and to store the resulting history in the context memory for use in subsequent operations for a particular input/output signal pair.