Abstract: To increase read reliability margins in read-only MRAM arrays, a complimentary pair of MRAM cells includes a first MRAM cell having a first resistance value within a first “high” resistance range RH and storing a logic “HI” value and a second “shorted” MRAM cell having a second resistance value within a second “minimal” resistance range Ro and storing a logic “LO” value. During manufacture and testing, MRAM cells that are assigned logic “LO” values are permanently shorted prior to distribution such that they permanently exhibit resistance values within the second “minimal” resistance range Ro. When reading the values stored within the complimentary pair of MRAM cells, a differential sense amplifier applies a common reference current across the first MRAM cell and the second “shorted” MRAM cell; by shorting cells with logic “LO” values, a system can reliably read logic values stored within the read-only MRAM array.

Abstract: A multi-bit MRAM cell includes at least a first MTJ device storing a first logic bit and a second MTJ device storing a second logic bit. The multi-bit MRAM cell is readable through application of a reference current across the multi-bit MRAM cell and comparison of a resultant output voltage with a plurality of reference voltages.