Abstract: A tributary time-space switch and a method of switching are provided having low memory requirements. The switch includes a number of inputs and outputs. Each of the inputs receives an input data stream carrying tributary payloads from an external input link that are capable of being individually switched in space and time. A write controller causes input columns of the input data stream to be written to a common buffer according to a write pointer. In parallel, a read controller causes the input columns to be read from the common buffer to output columns of an output data stream according to a read pointer. For each of the output columns, the read pointer selects an input column from a limited portion of the buffer that contains a set of the input columns that are capable of being switched in time to the corresponding output column according to a communication protocol.

Abstract: A hardware scheduler for a grooming switch with at least three switching stages accumulates a list of connection requests that cannot be granted given currently granted connection assignments. At a designated time, two data structures are dynamically built: an xRAM which records, for each output of a switch slice, which input is currently assigned to that output; and a yRAM which records, for each of the same outputs, the output of a second switch slice that is connected to a corresponding input of the second switch slice. Connections are assigned to satisfy the stored unassigned requests, by reassigning existing connection assignments using the xRAM and yRAM data structures.

Abstract: In a data communication circuit, data is multiplexed onto a communication link through multiple multiplexer stages and demultiplexed from the communication link through multiple demultiplexer stages in order that a clock signal applied to each multiplexing circuit need only be precisely distributed to a limited, high frequency portion of the circuit. Each circuit is clocked by a multiplying delayed locked loop bit clock generator. Where the number of parallel bits in the signal between the two stages is greater than two, the higher frequency stage coupled to the communication link is clocked by an N-phase overlapping clock. In the case of a multiplexer, the intermediate frequency signal is enabled in the higher frequency data multiplexer by concurrence of two clock phases.

Abstract: Two or more cross-connect ICs are interconnected. Each IC directly receives some, but not all, of the system inputs, and outputs to some, but not all, outputs. Each cross-connect IC has a switch matrix that has the same number of inputs as the system, and a lesser number of outputs that matches the number of outputs of the IC. Each cross-connect IC provides fanout of its direct inputs to a link to each other cross-connect IC. Thus, each IC receives inputs either directly, or from a fanout on another IC.

Abstract: An oscillating signal in an oscillator is caused to phase shift toward the phase of an input signal coupled to the oscillating signal. The resonant frequency of the oscillator is about equal to an integer multiple of the frequency of the input signal. The input signal may be generated in a pulse generator to have an input pulse duration less than or equal to that of the oscillating signal. The oscillator circuit may be used as a filter to filter pulse width variations or to filter jitter from a reference clock. The oscillator circuit may also serve as a buffer by amplifying the input signal. Phase interpolation can be obtained by coupling at least one input signal with at least one oscillating signal.

Abstract: Where links between a port module and plural switch fabric slices are of various lengths, a cell is transmitted from the port module to a switch fabric slice in response to a grant. The transmission is delayed by an amount based on a link round trip delay (RTD) value for the corresponding link between the port module and the switch fabric slice, and a predetermined global delay value. As a result of this delay, the cell arrives at the switch fabric slice at a fixed number of cell times (equal to the global delay value) after issuance of the grant, independent of any link lengths.

Abstract: Data cells of plural classes are transferred from input ports to output ports through a switch by storing the cells at each input port in class-specific virtual output queues (VOQ) within sets of VOQs associated with output ports, and providing credits to VOQs according to class-associated guaranteed bandwidths. When a cell is received at a VOQ having credits, a high-priority request for transfer is generated. If a cell is received at a VOQ that does not have any available credits, a low-priority request for transfer is generated. In response to requests, grants are issued to VOQ sets without regard to class, high-priority requests being favored over low-priority requests. When a grant is received for a particular VOQ set, an arbitrator selects a VOQ from the set, giving priority to VOQs having credits over VOQs without credits, and a cell from the selected VOQ is transferred.

Abstract: A switching fabric connects input ports to output ports. Each input has an input pointer referencing an output port, and each output has an output pointer referencing an input port. An arbiter includes input and output credit allocators, and an arbitration module (matcher). The input credit allocator resets input credits associated with input/output pairs and updates the input pointers. Similarly, the output credit allocator resets output credits associated with input/output pairs and updates the output pointers. The matcher matches inputs to outputs based on pending requests and available input and output credits. A scheduler schedules transmissions through the cross-bar switch according to the arbiter's matches.

Abstract: A semiconductor device which receives and transmits data at high speed is tested at operational speed at wafer sort. A probe card includes a high-speed interconnect that couples probe output bonding pads to probe input bonding pads. The high-speed interconnect connects a respective output of a transmitter in the die to a respective input of a receiver in the die while the probe card is connected to the die. A built in self test circuit in the die generates test patterns and compares them for accuracy. The test patterns are routed on the high-speed interconnect from the output of the transmitter to the input of the receiver allowing the data path through the receiver and transmitter in the die to be tested at operational speed before the die is assembled into a package.

Abstract: A scheduling algorithm is provided that may be implemented in a multi-stage switch requiring less switching elements than known switching architectures in order to increase bandwidth and to retain the non-blocking properties of the constituent switching elements for incoming traffic, including multicast traffic. A scheduling algorithm is also provided for incremental scheduling of connections being added or removed from the switch.

Abstract: An oscillating signal in an oscillator is caused to phase shift toward the phase of an input signal coupled to the oscillating signal. The resonant frequency of the oscillator is about equal to an integer multiple of the frequency of the input signal. The input signal may be generated in a pulse generator to have an input pulse duration less than or equal to that of the oscillating signal. The oscillator circuit may be used as a filter to filter pulse width variations or to filter jitter from a reference clock. The oscillator circuit may also serve as a buffer by amplifying the input signal. Phase interpolation can be obtained by coupling at least one input signal with at least one oscillating signal.

Abstract: In an integrated circuit, a data link relies on low swing differential signals. A push-pull driver circuit and a receiver circuit are both clocked from a common on-chip clock. A driver circuit includes an H-bridge of NMOS transistors and a line-to-line precharge circuit which reduces the power requirements of the circuit. A clocked repeater within the link may itself comprise a clocked receiver and an H-bridge driver with line-to-line precharge.

Abstract: A clock recovery circuit includes a sampler for sampling a data signal. Logic determines whether a data edge lags or precedes a clock edge which drives the sampler, and provides early and late indications. A filter filters the early and late indications, and a phase controller adjusts the phase of the clock based on the filtered indications. Based on the filtered indications, a frequency estimator estimates the frequency difference between the data and clock, providing an input to the phase controller to further adjust the phase so as to continually correct for the frequency difference.

Abstract: Improvements to scheduling of calls on a three stage network are provided. A multicast call is divided into plural portions which are scheduled separately. Protection channels are scheduled with primary channels by augmenting a call with an input switch containing the protection channel. Calls are scheduled on a set of free middle stage switches or time slots and are then added to a primary set. On occasion, the primary set is recompacted. Different sets of calls may be scheduled on different sets of middle stage switches or time slots, and each set may rely on a different scheduling algorithm.

Abstract: A grooming switch comprises plural input ports for receiving multi-time-slot input signals and plural output ports for forwarding multi-time-slot output signals. At least five switching stages alternate between time switching and space switching. The first stage is connected to the input ports, and the last stage is connected to the output ports. Each intermediate stage is connected to two other stages. Collectively, these stages perform compact superconcentration of the input signals, copying and distribution of the compact superconcentrated signals, and unicast switching of the distributed signals to form the output signals, resulting in a grooming switch that is rearrangeably non-blocking for arbitrary multicast traffic.

Abstract: A single-stage grooming switch is provided for switching streams of multiplexed traffic, such as SONET STS-48, in both time and space domains. In particular, the switch implements a distributed demultiplexing architecture for switching between any input timeslot to any output timeslot at a reduced layout size. Furthermore, the distributed demultiplexing architecture results in low latencies being associated with reconfiguration of output permutations on the order of nanoseconds.

Abstract: The timing circuit includes at least one delay element and its supply voltage is obtained from an active current source. The current source is a current mirror which is driven by a differential amplifier. The differential amplifier compares a voltage on the delay element supply line to a voltage on a current control node connected to a voltage controlled current source. An RC compensating circuit may be coupled to the current control node.

Abstract: In an integrated circuit, a data link relies on low swing differential signals. A push-pull driver circuit and a receiver circuit are both clocked from a common on-chip clock. A driver circuit includes an H-bridge of NMOS transistors and a line-to-line precharge circuit which reduces the power requirements of the circuit. A clocked repeater within the link may itself comprise a clocked receiver and an H-bridge driver with line-to-line precharge.

Abstract: An oscillating signal in an oscillator is caused to phase shift toward the phase of an input signal coupled to the oscillating signal. The resonant frequency of the oscillator is about equal to an integer multiple of the frequency of the input signal. The input signal may be generated in a pulse generator to have an input pulse duration less than or equal to that of the oscillating signal. The oscillator circuit may be used as a filter to filter pulse width variations or to filter jitter from a reference clock. The oscillator circuit may also serve as a buffer by amplifying the input signal. Phase interpolation can be obtained by coupling at least one input signal with at least one oscillating signal.

Abstract: In an integrated circuit, a data link relies on low swing differential signals. A push-pull driver circuit and a receiver circuit are both clocked from a common on-chip clock. A driver circuit includes an H-bridge of NMOS transistors and a line-to-line precharge circuit which reduces the power requirements of the circuit. A clocked repeater within the link may itself comprise a clocked receiver and an H-bridge driver with line-to-line precharge.