Abstract: A Fourier transform processor utilizing discrete circuits each of which is configurable for processing a wide range of sample sizes. A single pipeline supports multiplexed bi-directional transformations between for example the time and frequency domains. In an embodiment of the invention the Fourier Transform processor may be implemented as part of a digital signal processor (DSP). In this embodiment the DSP may implement both the discrete Fourier transform (DFT) and inverse discrete Fourier transform (IDFT) across a wide range of sample sizes and X-DSL protocols. Multiple channels, each with varying ones of the X-DSL protocols can be handled in the same session.

Abstract: An apparatus and method for reducing interference over a common communication medium, wired or wireless is provided. The apparatus reduces interference from a number of sources using a common architecture which may be used to service a modem pool or discrete modems which share the common communication medium. Interference due to near end cross-talk (NEXT), self-NEXT or echo, and far end cross-talk (FEXT) may all be substantially reduced or cancelled by the apparatus. Additionally, channel characteristics for individual data channels across the common communication medium may be determined. The apparatus provides support for multiple modem protocols including X-DSL protocols such as G.Lite, ADSL, VDSL, SDSL, MDSL, RADSL, and HDSL. The apparatus supports multiple line codes such as the discrete multi-tone (DMT) and carrier less AM/PM (CAP) line codes associated with X-DSL communications. The apparatus may be implemented in hardware, firmware or software.

Abstract: The current invention provides a DSP which accommodates multiple current X-DSL protocols and is further configurable to support future protocols. The DSP is implemented with shared and dedicated hardware components on both the transmit and receive paths. The DSP implements both the discrete Fourier transform (DFT) and inverse discrete Fourier transform (IDFT) portions across a wide range of sample sizes and X-DSL protocols. Multiple channels, each with varying ones of the X-DSL protocols can be handled in the same session. The DSP offers the speed associated with hardware implementation of the transforms and the flexibility of a software only implementation. Traffic flow is regulated in the chip using a packet based schema in which each packet is associated with a specific channel of upstream and downstream data. Header and control information in each packet is used to govern the processing of each packet as it moves along either the transmit path or receive path.

Abstract: A method and apparatus for digital subscriber line (xDSL) communications between one or more digital signal processors (DSPs) and analog front ends (AFEs) each coupled to corresponding subscriber line(s). The apparatus transports channels of data between subscribers and the DSP(s). The apparatus includes a bus for the transport of digital data, a DSP AFE interfaces. The DSP interfaces couples the DSP to the bus. The DSP interface accepts downstream channels of digital data from the DSP and transmits packets each associated with a corresponding one of the downstream channels to the bus. Each of the packets identifies a targeted AFEs coupled to a selected one of the subscriber lines. The AFE interfaces each couple an associated one of the AFEs to the bus. Each of the AFE interfaces transmits selected packets to a selected one of the subscriber lines for the transport to the subscriber.