Abstract: A microprocessor prediction circuit performs a first lookup of a fetch block start address (FBSA) in a fetch block predictor, detects a hit on a fetch block (FBlk), and generates a first FBlk descriptor (FBD). An instruction fetch circuit uses the first FBD to fetch the FBlk from an instruction cache. A control circuit receives an abort request associated with an instruction of the FBlk, determines an abort point separating the FBlk into former and latter portions, flushes the latter portion, allows the former portion to execute, and provides the abort point to the prediction circuit. The prediction circuit performs a second FBSA lookup, detects a hit on the same entry, and generates a second FBD describing at least the latter portion. The instruction fetch circuit uses the second FBD to re-fetch at least the latter portion, which the microprocessor executes, but does not re-execute the former portion.

Abstract: Each load/store queue entry holds a load/store physical address proxy (PAP) for use as a proxy for a load/store physical memory line address (PMLA). The load/store PAP comprises a set index and a way that uniquely identifies an L2 cache entry holding a memory line at the load/store PMLA when an L1 cache provides the load/store PAP during the load/store instruction execution. The microprocessor removes a line at a removal PMLA from an L2 entry, forms a removal PAP as a proxy for the removal PMLA that comprises a set index and a way, snoops the load/store queue with the removal PAP to determine whether the removal PAP is being used as a proxy for the removal PMLA, fills the removed entry with a line at a fill PMLA, and prevents the removal PAP from being used as a proxy for the removal PMLA and the fill PMLA concurrently.

Abstract: A power management system with differentiated power scaling including multiple activity monitors and a differentiated power manager. Each activity monitor counts performance benefit estimation events of each of multiple devices to determine performance benefit estimate values, each being a measure of relative power utilization efficiency of a corresponding device. The differentiated power manager periodically evaluates the performance benefit estimate values and dynamically adjusts relative power provided to each device to achieve differentiated power scaling based on the performance benefit estimate values. Additional power available during a higher performance mode may be distributed only to those devices with higher performance benefit estimate values. During any mode of operation, the power provided to those devices with lower performance benefit estimate values may be redirected to those devices with higher performance benefit estimate values.

Abstract: An out-of-order and speculative execution microprocessor that mitigates side channel attacks includes a cache memory and fill request generation logic that generates a request to fill the cache memory with a cache line implicated by a memory address that misses in the cache memory. At least one execution pipeline receives first and second load operations, detects a condition in which the first load generates a need for an architectural exception, the second load misses in the cache memory, and the second load is newer in program order than the first load, and prevents state of the cache memory from being affected by the miss of the second load by inhibiting the fill request generation logic from generating a fill request for the second load or by canceling the fill request for the second load if the fill request generation logic has already generated the fill request for the second load.

Abstract: A microprocessor includes a macro-op (MOP) cache (MOC) that holds MOC entries (MEs), including single-fetch block MEs (SF-MEs) and multi-fetch block MEs (MF-MEs), comprising MOPs decoded from architectural instructions. A prediction circuit generates fetch block (FBlk) start addresses (FBSAs) to make predictions of a sequence of FBlks fetched from an instruction cache and MEs fetched from the MOC. A back end detects that execution of a MOP of an MF-ME needs an abort and generates an abort request. A control circuit flushes all the MF-ME's MOPs and signals the prediction circuit to restart prediction at the MF-ME's FBSA. For each current FBSA of N current FBSAs used to make N predictions starting with the FBSA of the MF-ME, the prediction circuit ignores a hit on any MF-ME and instead, if the current FBSA hits on an SF-ME, predicts the SF-ME, and otherwise predicts a FBlk at the current FBSA.

Abstract: A system and method for a cache memory subsystem including a first-level cache (L1) and an N-way set associative second-level cache (L2) inclusive of L1, including receiving a physical memory line address (PMLA) for allocation into L2, using a set index of the PMLA to select a set of N ways of L2, for each way of the selected set of N ways, forming a physical address proxy (PAP) for the PMLA, in which each formed PAP includes the set index portion and the corresponding way that uniquely identifies a corresponding one of the selected set of N ways of L2, for each of the N formed PAPs, receiving a corresponding indicator of whether the formed PAP is resident in L1, and selecting one of the selected N ways of L2 having a corresponding indicator indicating that the corresponding one of the N formed PAPs is not resident in L1.

Abstract: A microprocessor includes a prediction unit (PRU) that continuously predicts a sequence of fetch block start addresses (FBSAs) that specify a corresponding sequence of fetch blocks (FBlks) in a program instruction stream and a macro-op cache (MOC) having MOC entries (MEs). The PRU installs into the MOC a loop body ME using a first FBSA value that specifies the loop body ME, instructs a fusion engine to build an unrolled loop multi-FBlk ME (ULP-MF-ME) using F copies of the loop body ME, installs the ULP-MF-ME using the same first FBSA value, detects a multiple-hit in the MOC on both the loop body ME and the ULP-MF-ME, and instructs a fetch unit to fetch from the MOC a number of copies of the ULP-MF-ME equal to an unrolled loop iteration count of the ULP-MF-ME and instructs the fetch unit to fetch the loop body ME until the loop exits.

Abstract: A microprocessor includes a prediction unit (PRU) that predicts a sequence of fetch blocks (FBlks) in a program instruction stream, a macro-op (MOP) cache (MOC) that comprises MOC entries (MEs), and a fusion engine. A FBlk comprises a sequential run of architectural instructions. An ME holds MOPs into which architectural instructions of one or more FBlks are decoded and includes training fields, updated by the PRU as the PRU predicts the ME in the program instruction stream. The PRU, in response to detecting that the training fields of an ME indicate the ME has been a loop body ME that has exhibited a consistent loop iteration count within the program instruction stream, requests the fusion engine to use F copies of the MOPs of the loop body ME to build in the MOC an unrolled loop multi-FBlk ME; F is at least two.

Abstract: A microprocessor includes a prediction unit (PRU) that predicts a sequence of fetch blocks (FBlks) in a program instruction stream, a macro-op (MOP) cache (MOC) that comprises MOC entries (MEs), a decode unit, and a fusion engine. Each ME indicates whether it is a single-FBlk ME (SF-ME) that holds MOPs associated with a single FBlk whose architectural instructions have been decoded into the MOPs of the SF-ME or a multi-FBlk ME (ME-ME) that holds MOPs associated with multiple FBlks whose architectural instructions have been decoded into the MOPs of the MF-ME. For each FBlk of one or more FBlks in the program instruction stream: the decode unit decodes the architectural instructions of the FBlk into MOPs, and the fusion engine builds a SF-ME in the MOC using the decoded MOPs, and the fusion engine builds a MF-ME in the MOC using the MOPs of a series of SF-MEs.

Abstract: A microprocessor includes a prediction unit (PRU) comprising a fetch block (FBlk) predictor (FBP) that predicts a sequence of FBlks, each FBlk having a corresponding fetch block start address (FBSA), and branch predictors; a macro-op (MOP) cache (MOC) includes MOC entries (MEs) including multi-FBlk MOC entries (MF-MEs) for holding MOPs decoded from instructions of multiple FBlks. The PRU detects a hit of a current FBSA on an MF-ME; performs a set of actions K times: looking up the current FBSA in the FBP and branch predictors to obtain outputs, using the outputs to predict a successor FBSA of a successor FBlk; and making the current FBSA the successor FBSA; and predicts that an FBSA of a successor FBlk to the MF-ME is the current FBSA resulting from performing K times the set of actions. K is a number of FBlks built into the MF-ME (alternatively times a loop unroll factor).

Abstract: A microprocessor includes a macro-op (MOP) cache (MOC) having MOC entries (MEs) holding MOPs. An instruction fetch circuit fetches from the MOC the MOPS of an ME for execution, and a back-end detects that a MOP of the ME is causing a need for an abort type within a predetermined subset of abort types. A control circuit uses a location within the ME of the abort-causing MOP to determine an abort point that separates the ME into a former portion and a latter portion, flushes the MOPs of the latter portion of the ME, and allows the MOPs of the former portion of the ME to execute. After the flush of the MOPs of the latter portion of the ME, the microprocessor re-fetches and executes the MOPs of the latter portion of the ME but does not re-execute the MOPs of the former portion of the ME.

Abstract: A microprocessor includes a prediction unit (PRU) that predicts a sequence of fetch blocks (FBlks) in a program instruction stream, a macro-op (MOP) cache (MOC) that comprises MOC entries (MEs), a fusion engine. An ME holds MOPs into which architectural instructions of one or more FBlks are decoded. The PRU detects a loop body ME within the program instruction stream, accumulates loop iteration count information about a series of instances of a loop on the loop body ME in the program instruction stream, updates a consistency counter of the loop body ME while accumulating the loop iteration count information, and in response to detecting that the consistency counter has reached a threshold, instructs the fusion engine to use F copies of the MOPs of the loop body ME to build in the MOC an unrolled loop multi-FBlk ME; F is a loop unroll factor that is at least two.

Abstract: A microprocessor includes a prediction unit (PRU) that predicts a sequence of fetch blocks (FBlks) in a program instruction stream and a macro-op (MOP) cache (MOC) that comprises MOC entries (MEs). An ME is either a single-FBlk ME (SF-ME) that holds MOPs associated with a single FBlk or a multi-FBlk ME (ME-ME) that holds MOPs associated with multiple FBlks. The PRU instructs a fusion engine to build a first MF-ME using the MOPs of a first set of two or more MEs when training fields of the first set of MEs indicate the first set appear as a first consistent sequence and instructs the fusion engine to build a second MF-ME using the MOPs of the first MF-ME and a third ME when the training fields of the first MF-ME indicate the first MF-ME and the third ME appear as a second consistent sequence within the program instruction stream.

Abstract: A microprocessor includes a physically-indexed physically-tagged second-level set-associative cache. A set index and a way uniquely identifies each entry. A load/store unit, during store/load instruction execution: detects that a first and second portions of store/load data are to be written/read to/from different first and second lines of memory specified by first and second store physical memory line addresses, writes to a store/load queue entry first and second store physical address proxies (PAPs) for first and second store physical memory line addresses (and all the store data in store execution case). The first and second store PAPs comprise respective set indexes and ways that uniquely identifies respective entries of the second-level cache that holds respective copies of the respective first and second lines of memory. The entries of the store queue are absent storage for holding the first and second store physical memory line addresses.

Abstract: A microprocessor includes a load/store unit that performs store-to-load forwarding, a PIPT L2 set-associative cache, a store queue having store entries, and a load queue having load entries. Each L2 entry is uniquely identified by a set index and a way. Each store/load entry holds, for an associated store/load instruction, a store/load physical address proxy (PAP) for a store/load physical memory line address (PMLA). The store/load PAP specifies the set index and the way of the L2 entry into which a cache line specified by the store/load PMLA is allocated. Each load entry also holds associated load instruction store-to-load forwarding information. The load/store unit compares the store PAP with the load PAP of each valid load entry whose associated load instruction is younger in program order than the store instruction and uses the comparison and associated forwarding information to check store-to-load forwarding correctness with respect to each younger load instruction.

Abstract: A prediction unit includes a first predictor that provides an output comprising a hashed fetch address of a current fetch block in response to an input. The first predictor input comprises a hashed fetch address of a previous fetch block that immediately precedes the current fetch block in program execution order. A second predictor provides an output comprising a fetch address of a next fetch block that immediately succeeds the current fetch block in program execution order in response to an input. The second predictor input comprises the hashed fetch address of the current fetch block output by the first predictor.

Abstract: A prediction unit (PRU) predicts a sequence of fetch blocks (FBlks). Branch predictors provide, in response to a FBlk start address (FBSA) lookup in combination with branch history state (BHS), information to predict branch history update information (BHUI) produced by the FBlk. A buffer stores accumulated BHUJ. A macro-op (MOP) cache (MOC) includes an unrolled loop multi-FBlk MOC entry (ULP-MF-ME) built from previously observed occurrences of a loop on a loop body of FBlks. A hit on the ULP-MF-ME predicts a current occurrence of a loop on the loop body. In parallel, for N initial iterations of the loop, the PRU updates the BHS with BHUI produced by each FBlk of the N initial iterations using information provided in response to a lookup and accumulates each BHUI into the buffer. The PRU updates the BHS using the accumulated BHUI for subsequent iterations of the loop to avoid more lookups.

Abstract: A cache memory subsystem includes virtually-indexed L1 and PIPT L2 set-associative caches having an inclusive allocation policy such that: when a first copy of a memory line specified by a physical memory line address (PMLA) is allocated into an L1 entry, a second copy of the line is also allocated into an L2 entry; when the second copy is evicted, the first copy is also evicted. For each value of the PMLA, the second copy can be allocated into only one L2 set, and an associated physical address proxy (PAP) for the PMLA includes a set index and way number that uniquely identifies the entry. For each value of the PMLA there exist two or more different L1 sets into which the first copy can be allocated, and when the L2 evicts the second copy, the L1 uses the PAP of the PMLA to evict the first copy.

Abstract: A die-to-die (D2D) interface between chiplets of a system on a chip (SoC) in which each of the chiplets are subdivided into slices. The D2D interface includes a transmission interface coupled between first and second chiplets, which includes a first transmission path for a first slice and a second transmission path for a second slice. The first chiplet includes receive circuitry which further includes a write interface and a read interface. The write interface stores data received from the first transmission path into a first FIFO using a first clock signal received via the first transmission path, and stores data received from the second transmission path into a second FIFO using a second clock signal received via the second transmission path. The read interface reads data stored in the first and second FIFOs using the first clock signal. The first and second transmission paths may be subject to different delays.

Abstract: A microprocessor includes a prediction unit (PRU) that predicts a sequence of fetch blocks (FBlks) in a program instruction stream, a macro-op (MOP) cache (MOC) that comprises MOC entries (MEs), and a fusion engine. An ME includes an expected next ME identifier and a counter, updated by the PRU as it predicts the ME in the program instruction stream, that is an indicator of consistency of sequence in the program instruction stream of the ME and an ME indicated by the expected next ME identifier. The PRU detects that each of the counters of N MEs indicate a highly consistent sequence of the N MEs and a final ME identified by the expected next ME identifier of a last ME in the sequence and instructs the fusion engine to use the MOPs of the N MEs and of the final ME to build in the MOC a sequential multi-FBlk ME.