Abstract: An integrated circuit, including a configurable scan architecture used for an integrated circuit test procedure and quality control. The configurable scan chain architecture has the capability of being reconfigured to one of a variety scan chain architectures based on the constraints of the integrated circuit and the testing device. The present invention minimizes the integrated circuit test time by reconfiguring the scan architecture depending on certain constraints such as the latching frequency, the predetermined I/O frequency, the number of available integrated circuit I/O pins, the number of pins required for a proposed scan architecture, and the number of available pins on the testing device. The configurable scan architecture receives configuration signals which indicate which scan chain architecture should be configured on the integrated circuit that is being tested.
September 4, 2001
Date of Patent:
November 14, 2006
Ajay Khoche, Jochen Rivoir, David H. Armstrong