Abstract: In one embodiment, a mating circuit assembly is coupled and decoupled to a system by 1) mechanically and electrically coupling at least a first interposer, mounted on at least one of first and second substrates, to the mating circuit assembly. The mechanical and electrical coupling is accomplished using at least first and second spring mechanisms, with the first and second spring mechanisms being mounted between the connector housing and respective ones of the first and second substrates. At least one of the first and second substrates transmits signals between the first interposer and the system. The first interposer is electrically and mechanically decoupled from the mating circuit assembly by creating a vacuum between the connector housing and at least one of the first and second substrates. Other embodiments are also disclosed.

Abstract: A method for testing a device-under-test (DUT) includes examining a test data file that includes test data for testing the structure, functionality and/or performance of the DUT. The method also includes separating a first plurality of data units from a second plurality of data units contained in the test data file. The first plurality of data units correspond to a first plurality of DUT pins, and the second plurality of data units correspond to a second plurality of DUT pins.

Abstract: A method and apparatus for verifying an integrated circuit device test for testing an integrated circuit device on an automated tester is presented. An integrated circuit device simulator simulates a flawed integrated circuit device that models one or more known flaws, or physical defects, in an assumed good integrated circuit device design. A tester simulator simulates the integrated circuit device test which sends stimuli to, and receives responses from, the simulated flawed integrated circuit device. A test analyzer then determines whether the simulated test of the simulated flawed integrated circuit device detected the flaws in the simulated flawed integrated circuit device and properly failed the simulated flawed integrated circuit device.

Abstract: Structural testing can lead to high and abnormal current surges. Disclosed herein are methods for designing and testing an IC so that current surges therein may be minimized while the IC is being tested. One disclosed way to minimize current surges is by gating out shift induced node state transitions. Another disclosed way to minimize current surges is to operate two or more of an IC's scan chains in parallel, but out-of-phase.

Abstract: A system and method that enables testing of circuitry using an externally generated signature. An external tester is arranged external to a device under test (DUT). Such external tester is operable to input test data to the DUT, receive output data from the DUT, and generate a signature for at least a portion of such received output data. The external tester compares the generated signature with an expected signature to determine whether the DUT is functioning as expected. If the generated signature fails to match an expected signature, then error data can be written to an error map log. Preferably, further interaction with the DUT is not required after detecting that a generated signature fails to match an expected signature in order to perform such error evaluation. Thus, error evaluation can be performed concurrently with testing of the DUT. Mask data may be stored in a compressed form, and decompressed and used for masking certain non-deterministic output bits in generating the signature.

Abstract: An article of manufacture may include a dielectric having a top surface and a bottom surface. The top surface provides a planar surface corresponding to a mating surface of test equipment. The bottom surface has a relief pattern that is formed to straddle components extending above a surface of a load board for a circuit tester. Also disclosed are methods and apparatus that use this and other dielectric plates to mate test equipment to a load board of a circuit tester.

Abstract: A parallel calibration system for an electronic circuit tester comprises test and measurement electronics, a test fixture coupled to the test and measurement electronics, the test fixture comprising clock reference circuitry and clock distribution circuitry, a device under test interface, and a plurality of calibration boards coupled to the device under test interface, wherein the plurality of calibration boards and the clock distribution circuitry simultaneously test the signal paths of a plurality of test channels.