Patents Assigned to Verigy Pte Ltd
  • Patent number: 7231573
    Abstract: A delay management system in a computer system includes a delay manager and a first storage element that stores a delay time. The delay manager is configured to receive a series of delay values and respond to each delay value in the series of delay values by providing a corresponding delay time value. The delay time is updated to the corresponding delay time value if the corresponding delay time value is greater than the delay time.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: June 12, 2007
    Assignee: Verigy Pte. Ltd.
    Inventors: Alan Howard Davis, John Freeseman
  • Patent number: 7213803
    Abstract: A clamp having a frame and a latch member mounted within the frame so that the latch member is translatable along a displacement axis and rotatable about the displacement axis. A guide pin mounted to the frame engages a channel operatively associated with the latch member. An actuator mounted to the frame and operatively associated with the latch member translates the latch member along the displacement axis. The engagement of the guide pin and channel causes the latch member to be rotated about the displacement axis as the latch member is translated along the displacement axis.
    Type: Grant
    Filed: January 24, 2005
    Date of Patent: May 8, 2007
    Assignee: Verigy Pte. Ltd.
    Inventor: Donald Wai-Chung Chiu
  • Patent number: 7206710
    Abstract: In one embodiment, a request to perform a calibration process for automated test equipment (ATE) is received. The request is associated with a calibration parameter set. After receiving the request, one or more signatures for calibration data corresponding to the calibration parameter set are derived, and a determination is made as to whether calibration data corresponding to the signature(s) has already been generated. Thereafter, an incremental set of calibration data is generated, with the generated calibration data i) corresponding to the signature(s), but ii) not having already been generated. In another embodiment, a request to perform a calibration process for ATE is received, and the request is associated with specified test setups. An incremental set of calibration data corresponding to the specified test setups is then generated.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: April 17, 2007
    Assignee: Verigy Pte. Ltd.
    Inventors: Zhengrong Zhou, Mike Millhaem
  • Patent number: 7193854
    Abstract: A heat sink assembly for cooling a component is disclosed, the heat sink assembly comprising a printed circuit board; a clamp plate; a waterblock cooling device; and a force attachment component to attach the clamp plate and the waterblock cooling device with the printed circuit board in contact with the waterblock cooling device and the clamp plate. A method is disclosed for connecting together a heat sink assembly and a component, the method comprising inserting standoffs of a clamp plate through passage holes in a printed circuit board; inserting the standoffs of the clamp plate through clearance holes in a waterblock cooling device; and positioning a spring component in contact with the clamp plate and the waterblock cooling device so as to position the printed circuit board in contact with the waterblock cooling device and the printed circuit board in contact with the clamp plate.
    Type: Grant
    Filed: May 2, 2005
    Date of Patent: March 20, 2007
    Assignee: Verigy Pte. Ltd
    Inventors: Paul Bonomo, John Andberg
  • Patent number: 7194373
    Abstract: Methods and systems for controlling device testing are disclosed. In one embodiment, the system comprises a local controller having a slave mode and a control mode, when in the control mode, the local controller to control testing of a device and to initiate one or more test instructions to be applied to the device, and when in the slave mode, to pass through a remote test instruction received from a remote controller to a tester. The system further comprises the tester, communicatively coupled to the local controller, to apply one of the one or more test instructions and the remote test instruction to the device.
    Type: Grant
    Filed: October 14, 2003
    Date of Patent: March 20, 2007
    Assignee: Verigy Pte. Ltd,
    Inventor: Robert S. Kolman
  • Patent number: 7190217
    Abstract: In one embodiment, ground separation is provided between first and second grounded environments by configuring first and second op-amps of the second grounded environment as buffers, configuring a third op-amp of the second grounded environment to output a difference of its inputs, and coupling the inputs of the third op-amp to outputs of the first and second op-amps. A signal sensing input of each of the first and second op-amps is biased by 1) coupling the signal sensing input to a respective one of first and second impedances, and 2) coupling the first and second impedances to a ground of the first grounded environment. A signal from the first grounded environment is then provided to the signal sensing input of the first op-amp. Related apparatus is also disclosed.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: March 13, 2007
    Assignee: Verigy Pte. Ltd.
    Inventor: Diane Dai
  • Patent number: 7190583
    Abstract: Although various embodiments of the method and apparatus of the present invention have been illustrated in the accompanying Drawings and described in the foregoing Detailed Description, it will be understood that the invention is not limited to the embodiments disclosed, but is capable of numerous rearrangements, modifications and substitutions without departing from the spirit of the invention as set forth herein.
    Type: Grant
    Filed: August 29, 2005
    Date of Patent: March 13, 2007
    Assignee: Verigy Pte Ltd
    Inventors: Tracy W. Fendley, Rick T. Euker, Brent W. Thordarson
  • Patent number: 7184469
    Abstract: A method for injecting test jitter in a data bit stream comprises modulating first and second voltage generators to control a rise and fall times of an output signal, respectively. A pair of input voltages are received by a differential pair. At least one current sink device is operated using a first control voltage provided by at least one of the voltage generators to provide an output voltage in response to the input voltages received by the differential pair. A plurality of current sources are operated to provide the output signal using a reference voltage provided by one of the voltage generators in response to the input voltages received by the differential pair, wherein simultaneous variation of the rise and fall times together with the input voltages define the output signal and jitter output by the current sink device and the current sources.
    Type: Grant
    Filed: February 6, 2003
    Date of Patent: February 27, 2007
    Assignee: Verigy Pte. Ltd.
    Inventors: Francis Joseph, Klaus D. Hilliges, Cheryl L. Owen
  • Patent number: 7181660
    Abstract: Input to a device under test (DUT) is reconstructed. For each trigger cycle of a tester in which data is to be input to the DUT stimulus, data is prepared to be placed as stimulus on pins of the DUT. Response information obtained from the DUT during a previous trigger cycle is used to construct formatting information used to adjust a value of the stimulus data. Reconstruction information sufficient to reconstruct the stimulus data is stored. The reconstruction information includes the formatting information. The reconstruction information is used to reconstruct the stimulus data placed on the pins of the device under test.
    Type: Grant
    Filed: July 26, 2002
    Date of Patent: February 20, 2007
    Assignee: Verigy Pte. Ltd.
    Inventors: Alan S. Krech, Jr., Stephen Dennis Jordan, Hsiu-Huan Shen
  • Patent number: 7180392
    Abstract: A novel coaxial DC block with circumferential capacitive shielding is presented. The coaxial DC block includes an inner DC block electrically couplable to a first inner conductor of a first length of coaxial cable and electrically couplable to a second inner conductor of a second length of coaxial cable. The inner DC block provides a capacitance which capacitively couples the first inner conductor to the second inner conductor and blocks a first frequency range of interest. The inner DC block is electrically sealed and shielded by a capacitive sleeve that is concentrically arranged to form a Faraday cage around the inner DC block. The capacitive sleeve is electrically couplable to a first outer conductor of the first length of coaxial cable and electrically couplable to a second outer conductor of the second length of coaxial cable.
    Type: Grant
    Filed: June 1, 2004
    Date of Patent: February 20, 2007
    Assignee: Verigy Pte Ltd
    Inventors: Victor Matthew Grothen, Mark Robert Reiland
  • Patent number: 7181663
    Abstract: A wireless integrated circuit test method and system is presented. The invention allows testing of one or more integrated circuits configured with a wireless interface and a test access mechanism which controls input of test data received over a wireless connection from a test station to test structures which test functional blocks on the integrated circuit. Via the wireless connection, multiple integrated circuits or similarly equipped devices under test can be tested simultaneously. The invention also enables concurrent testing of independently testable functional blocks on any given integrated circuit under test.
    Type: Grant
    Filed: March 1, 2004
    Date of Patent: February 20, 2007
    Assignee: Verigy Pte, Ltd.
    Inventor: Andrew S. Hildebrant
  • Patent number: 7181358
    Abstract: In a method for assigning test numbers, current testflow context information is maintained during execution of a testflow. The information is maintained as an array of one or more context values. Upon execution of a subtest in the testflow, a map of linked data nodes is indexed using a key formed from 1) a numeric identifier of the subtest, and 2) the array of context values. If a data node corresponding to the key exists in the map and is associated with a test number, the data node's test number is assigned to a result of the subtest; else, a new test number is assigned to the result of the subtest, and the new test number is associated with a data node that is linked in the map. A test number database, and a test number engine for satisfying calls for test numbers, are also disclosed.
    Type: Grant
    Filed: May 5, 2004
    Date of Patent: February 20, 2007
    Assignee: Verigy Pte. Ltd.
    Inventors: Robert S. Kolman, Reid Hayhow