Abstract: In one embodiment, a semiconductor test control system includes a computer system having a plurality of hardware resources; a hypervisor installed on the computer system; and a test floor controller installed on the computer system. The hypervisor virtualizes the hardware resources and provides each of at least one virtual appliance with access to a respective virtual set of the hardware resources. Each virtual set of the hardware resources places its respective virtual appliance in controlling communication with at least a first aspect of a semiconductor test system, thereby enabling the respective virtual appliance to test a respective type of semiconductor device. The test floor controller is in controlling communication with i) at least a second aspect of the semiconductor test system, and ii) each of the at least one virtual appliance.

Abstract: An active routing circuit. In representative embodiments, the active routing circuit includes a channel switch which includes a transceiver and a switch. The transceiver has first data line, second data line, drive/receive control line, and receiver select control line. The switch has first contact connected to first data line, second contact connected to second data line, and switch control line. In a driver mode, the transceiver can receive data from first data line and output that data to second data line, and in receiver mode, can receive data from second data line and output that data to first data line. The transceiver can switch between driver mode and receiver mode in response to a signal. Data received from the second data line can be blocked in response to another signal. The switch can shift between connecting and disconnecting first contact to/from second contact in response to yet another signal.

Abstract: A method runs a simulation. The method comprises receiving a selection of a device. The device is one of a prober used in wafer testing and a handler used in package testing. The method comprises receiving at least one parameter for a set of parameters for the simulation. The method comprises running the simulation by executing commands to be performed as if the device were present. A controller supplies the set of commands. Results from the simulation indicate a performance of the controller.

Abstract: As a scan pattern is shifted out of a scan chain, the scan pattern is evaluated in real-time for the existence of a logic condition. A reference to a portion of the scan pattern that is currently being evaluated is maintained. Upon identifying the existence of the logic condition when the reference has a predetermined relationship to a stored value, the stored value is overwritten using the reference. The stored value is then used to estimate the position of a stuck-at defect in the scan chain.

Abstract: A communication circuit for providing a bi-directional data transmission over a signal line, thereby receiving a first digital data stream and transmitting a corresponding first signal into a near end of a signal line to a remote device, the remote device being connected to a far end of the signal line, receiving a second signal at the near end of the signal line from the remote device and deriving a second digital data stream therefrom, having a replica generator for providing, in response to the first digital data stream or a signal derived therefrom, a replica signal, and an extraction circuit for extracting the second digital data stream from the second signal in response to the replica signal and a comparator signal deduced from the near end of the signal line and an automatic test equipment having a plurality of communication circuits each providing a bi-directional data transmission.

Abstract: A method for operating a secure semiconductor IP access server to support failure analysis. A client presents a test failure and failure type to an automated server which traverses an electronic product design, definition, and test database to report specifically those components and interconnect likely to cause the failure with geometrical information which may be displayed on the client. Other aspects of semiconductor IP are protected by the server by limiting the trace mechanism and renaming components.

Abstract: A re-configurable test circuit for use in an automated test equipment includes a test circuit, a test processor and a programmable logic device. The pin electronics circuit is configured to interface the re-configurable test circuit with a DUT. The test processor includes a timing circuit configured to provide one or more adjustable-timing signals having adjustable timing. The programmable logic device is configured to implement a state machine, a state sequence of which depends on one or more input signals received from the pin electronics circuit, to provide an output signal, which depends on a current or previous state of the state machine, to the pin electronics circuit in response to the signal(s) received from the pin electronics circuit. The test processor is coupled to the programmable logic device to provide at least one of the adjustable-timing signal(s) to the programmable logic device to define timing of the programmable logic device.

Abstract: A device for processing data adapted for being converted between an analog format and a digital format, the device having a scrambling unit adapted for scrambling the data based on at least a part of the data to thereby decorrelate the data in the analog format with respect to the data in the digital format.

Abstract: A system (100) for detecting an electrostatic discharge event with respect to a device (110) to be monitored comprises a current measurement device (140) configured to measure a current flowing via a power supply connection (120) connecting the device to be monitored with the power supply to obtain a current measurement signal representing the current or a current component. Alternatively, a current flowing through a protective earth connection (180) connecting the device to be monitored with the protective earth is measured to obtain the measurement signal. The system comprises an electrostatic discharge event detector configured to detect an electrostatic discharge event in response to a pulse of the current measurement signal. The system may optionally comprise data processing of current measurement signals or values.

Abstract: An embodiment of a state machine for generating a pseudo-random word stream, each word of the word stream including a plurality of subsequent bits of a pseudo-random bit sequence includes a plurality of clock registers and a feedback circuit coupled to the registers and adapted to provide a plurality of feedback signals to the registers based on a feedback function and a plurality of register output signals of the registers, wherein the state machine is configured such that a first word defined by the plurality of register output signals includes a first set of subsequent bits of a pseudo-random bit stream and such that a subsequent second word defined by the plurality of register output signals includes a second set of subsequent bits of a pseudo-random bit stream.

Abstract: A method for injecting timing irregularities into test patterns self-generated by a device under test (DUT) includes obtaining timing irregularities, receiving the test patterns generated by the device under test driven from output drivers of the DUT, injecting the timing irregularities into the test patterns to generate test patterns with timing irregularities injected therein, and applying the test patterns with timing irregularities injected therein to input receivers of the DUT. A tester is configured to test loopback functionality of a device under test (DUT) utilizing a timing irregularities injection apparatus which receives timing irregularity data readable by the tester and test data generated by the DUT, and injects the timing irregularity data into the test data for application to the DUT.

Abstract: A system includes at least one of a first generator, at least two of a second generator, and a load board. The at least one of a first generator one of receives and transmits analog signals. The at least two of a second generator one of receives and transmits digital signals. The load board is disposed between the first generator and the second generators and electrically coupled therebetween to calibrate parameters relating to communications. The load board includes a direct path for each of the analog signals between the at least one of the first generator and a corresponding number of devices under test and for each of the digital signals between the at least two of the second generator and a corresponding number of devices under test.

Abstract: In a method for determining a number of possible hold time faults in a scan chain of a DUT, an environmental variable of the scan chain is set to a value believed to cause a hold time fault in the scan chain, and then a pattern is shifted through the scan chain. The pattern has a background pattern of at least n contiguous bits of a first logic state, followed by at least one bit of a second logic state, where n is a length of the scan chain. The number of possible hold time faults in the scan chain can be determined as a difference between i) a clock cycle when the at least one bit is expected to cause a transition at an output of the scan chain, and ii) a clock cycle when the at least one bit actually causes a transition at the output of the scan chain. If a value of the environmental variable at which the scan chain operates correctly can be determined, the location of one or more hold time faults can also be determined.

Abstract: An excitation signal generator (“ESG”) is described. The ESG generates an minimized excitation signal for use in a test system to generate a functional model of a device under test (“DUT”) where extreme values of the minimized excitation signal are increased toward a central value without changing the power spectrum at the DUT.

Abstract: A method for data logging from inside a semiconductor device, yielding timing performance information about the logic behind each and every flip-flop in the scan chain and displaying the sensitivity of certain flipflops to speed related manufacturing defects. The method comprises steps for testing, measuring, storing, and analyzing records for frequency characterization of complex digital semiconductors.

Abstract: A data processing unit has a time information provider for processing a clock or a strobe signal, configured to provide a digitized clock or strobe time information on the basis of the clock or strobe signal and at least one data extraction unit, coupled to the time information provider and configured to select data from a sequence of data samples of a data signal depending on the digitized clock or strobe time information.

Abstract: For determining a minimum/maximum of a plurality of binary values a bit position in the plurality of binary values is determined subsequent to which all bit values are the same. From the plurality of binary values those binary values are selected the bit values of which at the bit position determined in the preceding step and all subsequent positions, if any, has a predetermined value. The preceding steps are then repeated until only one binary value remains which is provided as the minimum or maximum.

Abstract: A signal distribution structure for distributing a signal to a plurality of devices includes a first signal guiding structure including a first characteristic impedance. The signal distribution structure also includes a node, wherein the first signal guiding structure is coupled to the node. The signal distribution structure includes a second signal guiding structure including one or more transmission lines. The one or more transmission lines of the second signal guiding structure are coupled between the node and a plurality of device connections. The second signal guiding structure includes, side-viewed from the node, a second characteristic impedance which is lower than the first characteristic impedance. The signal guiding structure also includes a matching element connected to the node.

Abstract: A repetitive bit value pattern associated to a predetermined bit position of a sequence of data words, the data words having two or more bits in a bit order, a bit position describing a position within the bit order being indicative of a value represented by the bit at the bit position, can be determined from program loop information, the program loop information having a program expression for determining an updated data word of the sequence of data words. Using the predetermined bit position, a sequence length value associated to the predetermined bit position is determined. The program expression is evaluated for a number of loop iterations indicated by the sequence length value, to obtain updated bit values associated to the predetermined bit position. The repetitive bit value pattern is determined using the updated bit values of the number of loop iterations.

Abstract: A test system for performing tests on devices under test (DUTs) includes a storage device storing test data for performing the tests on the DUTs, a shared processor for generating the test data, storing the test data in the storage device and generating a test control signal including one or more test instructions for executing the tests, and, for each DUT, a dedicated processor configured to receive a test control signal from the shared processor, and in response to the test control signal, transfer the test data for one of the test instructions to the DUT to execute that test instruction and verify the completion of that test instruction.