Abstract: A dataset is divided into overlapping logical pages, each associated with a different page index. A graphical display window is then filled with data corresponding to a current page offset which is mapped into a subset of data in a logical page corresponding to a current page index. Events associated with user operation of navigation controls are intercepted, and upon determining that an event causes updating of the current page offset to a defined position within the currently indexed page, the current page index and offset are transparently mapped to a new page index and offset. The window may be associated with a scrollbar grip, and upon intercepting an event associated with operation of the grip, the position of the grip is scaled by multiplying it by a scaling factor. The current page index is then set to the index of a logical page that scales to the grip's position.

Abstract: A method and apparatus for filtering failures due to must-repair rows or columns from a memory test fail summary image includes current available redundant row failure counts respectively associated with rows of a memory device and current available redundant column failure counts associated with columns of the device. Respective failure counts are preloaded with the respective values of redundant rows and columns available for repairing the device. When failures in memory cells of the device are encountered, either during test, or during scan of an earlier generated error image, the row and column failure counts associated with the rows and columns containing the memory cell failures are decremented. At the end of a test, the value of the failure counts indicates whether the corresponding row or column contain any failures at all, whether the corresponding row or column is designated as a “must-repair” row or column, and otherwise how many errors the corresponding row or column contain.

Abstract: A method and a corresponding system for converting a digital signal to an analog signal using a plurality of signal sources, preferably current sources, at least two of the signal sources being equal output signal magnitude sources, said method including controlling the equal output signal magnitude sources by a logic circuit, providing a digital input signal to the logic circuit, the digital input signal being derived from the digital signal to be converted, filtering the digital input signal using a filter, the filter having a filter order being adaptable by the logic unit in response to needs concerning bandwidth of the conversion, and summing the outputs of the equal output signal magnitude sources to contribute to the analog signal.

Abstract: In an embodiment, there is disclosed a system for derivation of missing data objects from test data. The system may include a data populator having code for: (1) generating data objects from the test data, (2) arranging the data objects in a tree structure, (3) deriving the missing data objects from the tree structure, and (4) populating the missing data objects into the tree structure; a data model in communication with the data populator; and a plurality of clients in communication with the data model. In an embodiment, a method of derivation of missing data objects from test data is disclosed. The method may include generating data objects from the test data; arranging the data objects in a tree structure; deriving the missing data objects from the tree structure; and populating the missing data objects into the tree structure. Other embodiments are also disclosed.

Abstract: In one embodiment, a mock wafer for calibrating automated test equipment includes a printed circuit board having a number of interconnect areas, with each interconnect area having a pair of mock die pads that are coupled via a connecting trace. In another embodiment, a method for calibrating automated test equipment (ATE) may include coupling the mock wafer to the ATE, and then causing the ATE to i) index the mock wafer with respect to a test head connector, ii) couple a number of probes or the test head connector to a number of the mock wafer's mock die pads, iii) transmit a test signal between a pair of the probes that are coupled via a pair of mock die pads and connecting trace of the mock wafer, and iv) calibrate a selected signal path or paths of the ATE by recording a characteristic of the transmitted test signal.

Abstract: Disclosed are various embodiments of electrical coupling apparatuses and methods. In one embodiment, an electrical coupling apparatus is provided having a first contact array on a card, where the first contact array is located at a first predefined position relative to an insertion edge of the card. The apparatus also includes a flexible printed circuit having a second contact array corresponding to the first contact array, where the second contact array is positioned in alignment with the first contact array. A compliant interposer material is positioned between the first and second contact arrays, the compliant interposer material electrically coupling respective pairs of contacts in the first and second contact arrays. Also, the insertion edge is configured to be inserted into a receptacle, the second contact array being positioned relative to the insertion edge so as to mate with a corresponding contact array in the receptacle when the insertion edge is inserted into the receptacle.

Abstract: Methods for configuring the capabilities of electronic systems containing printed circuit boards are provided. One such method comprises: providing an initial configuration describing a first set of capabilities corresponding to each PCB as currently configured; modifying the initial configuration through a user interface to produce a new configuration describing a second set of capabilities corresponding to each PCB after upgrade; saving the initial configuration as modified by the user interface to be the new configuration; and configuring the plurality of PCBs according to the new configuration. Systems are also provided.

Abstract: A method and apparatus for modulating a digital input signal is disclosed. The digital input signal is partitioned into a less-significant bit signal and a more-significant bit signal. A lower-order modulation of the less-significant bit signal is performed to generate an intermediate output signal. The intermediate output signal is appended to the more-significant bit signal to form an intermediate input signal. A higher-order modulation of the intermediate input signal is performed to generate a digital output signal. The higher-order modulation is of an order higher than the lower-order modulation. A phase-locked loop using the method and apparatus is disclosed.

Abstract: In one embodiment, an electronic device is tested using automated test equipment (ATE) by 1) storing different vectors of scan load data in memory of the ATE; 2) storing a scan unload subroutine in the memory of the ATE; 3) stimulating the electronic device by retrieving the different vectors of scan load data and applying them to the electronic device; and 4) capturing responses to the different vectors by repeatedly calling the scan unload subroutine, and in response thereto, storing different vectors of scan unload data in the memory.

Abstract: In a device for measuring the properties of a device under test connected by a signal transmission path having reciprocity, a terminal on the device under test side of the signal transmission path is opened; pulse signals are transmitted to a terminal on the measuring apparatus side of the signal transmission path; the transmitted pulse signals are monitored and spectrum analyzed on the measuring apparatus; the pulse signals reflected from a terminal on the device under test side of the signal transmission path are monitored and spectrum analyzed on the measuring apparatus; and the frequency properties of propagation delay of the signal transmission path are found by referring to the coefficient obtained based on the impedance of the resistance load, the spectrum of the transmitted pulse signals, and the spectrum of the reflected pulse signals. The effect of an error is eliminated from the measuring results using the resulting frequency properties or propagation delay in actual measurement.

Abstract: In one embodiment, a selection of plural testflows is first obtained. Each testflow specifies how automated test equipment (ATE) should test at least one device. Calibration information is then identified for each of the testflows, and redundancies in the identified calibration information are eliminated to compile a set of non-redundant information for performing a focused calibration over the ATE and selected testflows.

Abstract: In one embodiment, an automated circuit test system is calibrated by electrically coupling a first calibration unit between a plurality of drivers and comparators of the test system, and then executing an AC timing calibration procedure to determine a timing delay for each of a first set of relationships. A second calibration unit is then electrically coupled between the plurality of drivers and comparators, and an AC timing calibration procedure is executed to determine a timing delay for each of a second set of relationships. The first and second calibration units comprise fixed wiring paths that respectively couple pairs of the drivers and comparators in accord with the first and second sets of relationships. A set of equations is solved based on the timing delays and driver/comparator relationships to determine relative timing errors introduced by signal paths of the test system including the drivers and comparators.

Abstract: A method for testing an electronic component. The method includes connecting the electronic component to a test machine; specifying search range limits, low-to-high transition edge and high-to-low transition edge found criterion, and number of outcomes in a trial including multiple tests specified as proof of low-to-high transition or as high-to-low transition; computing values for initial trial parameters; if low-to-high transition edge not found: executing a low-to-high trial and adjusting trial parameter values based on results of step executing low-to-high trial; if high-to-low transition edge not found: executing high-to-low trial; and if either low-to-high or high-to-low transition edge not found: adjusting trial parameter values based on results of step executing high-to-low trial and repeating above steps beginning with the step having the condition if low-to-high transition edge has not been found.

Abstract: Systems and methods of allocating device testing resources are described. In one aspect, a system for allocating m resources for testing devices to n sites of a probe card configured to electrically connect to respective test site locations on a substrate, where m and n are integers and m<n, is described. The system includes a configurable interconnection network that includes a plurality of connections between resources and the probe card sites. The connections enable each test site location to be connected to at least one of the resources over a minimum number of touchdowns of the probe card onto the test sites. Each of the resources is connectable to at most a number of the probe card sites equal to the minimum number of touchdowns. A method of allocating m resources for testing devices to n sites of a probe card configured to electrically connect to respective test site locations on a substrate, where m and n are integers and m<n, also is described.

Abstract: A rotatable or translatable carousel configured to facilitate electrical or electronic testing of Devices Under Test (DUTs) in combination with an insertion handler and a test head is disclosed. The carousel is configured to be placed on a test head of a tester in a first position with a first Device under Test (DUT) (such as a system-on-a-chip (SOC) integrated circuit (IC)) loaded in a first test position of the carousel. A first electrical or electronic test is performed on the first DUT at the first position, after which the carousel is advanced to a second position and a second DUT is loaded in a second test position of the carousel. While the carousel is positioned at the second position, the first test is performed on the second DUT and a second electrical or electronic test is performed on the first DUT.

Abstract: A sequencer unit includes a first instruction processing unit, an instruction buffer and a second instruction processing unit. The first instruction processing unit is adapted for receiving and processing a stream of instructions, and for issuing, in case data is required by a certain instruction, a corresponding data read request for fetching said data. Instructions that wait for requested data are buffered in the instruction buffer. The second instruction processing unit is adapted for receiving requested data that corresponds to one of the issued data read requests, for assigning the requested data to the corresponding instructions buffered in the instruction buffer, and for processing said instructions in order to generate an output data stream.

Abstract: In one embodiment, a resource matrix is provided with a first set of pins, a second set of pins, and at least one programmable switching circuit. The first set of pins electrically couples the resource matrix with a tester resource. The second set of pins electrically couples the resource matrix with a plurality of test areas. The at least one programmable switching circuit selectively couples each one of the first set of pins to different ones of the second set of pins. In one embodiment, the at least one programmable switching circuit includes a set of multiplexers. In another embodiment, the at least one programmable switching circuit includes a set of LIMMS. In another embodiment, a system is disclosed for testing a plurality of test areas with a tester resource and a resource matrix. Methods for routing signals between a tester resource and plurality of test areas are also disclosed.

Abstract: There is provided a method that includes (a) sampling a data signal and a clock signal by applying strobes for obtaining a corresponding bit values each for the data signal and for the clock signal, each of the strobes having a different phase offset with respect to a tester clock signal, (b) deriving first comparison results for the bit values of the data signal by comparing the bit values of the data signal each with an expected data bit value of expected data, (c) deriving second comparison results for the bit values of the clock signal by comparing the bit values of the clock signal each with an expected clock bit value, (d) deriving for the strobes combined comparison results by applying logical operations each on pairs of corresponding first and second comparison results, and (e) deriving a test result based on the combined comparison results.

Abstract: Monitoring a spectrum of an inter-leaved signal by a signal generator which inter-leaves two DAC outputs with the same sampling rate, while adjusting the output offset level of each DAC, the output amplitude level of each DAC, the output selection timing of each DAC, and the output renewal timing of each DAC.

Abstract: In one embodiment, a method provides scan patterns to an electronic device having BIST hardware. The BIST hardware has production and diagnostic test modes, and the device outputs one or more response signatures in the production test mode and outputs raw response data in the diagnostic test mode. In production test mode, the method uses ATE to 1) provide a first series of scan test patterns to the BIST hardware, and 2) capture and compare response signatures to expected response signatures, to identify a number of failing scan test patterns. The method then uses the ATE to identify a number of unique labels associated with the failing patterns. In diagnostic test mode, the method uses the ATE to 1) provide a second series of scan test patterns to the BIST hardware, and 2) capture raw response data. The scan test patterns in the second series correspond to the identified labels.