Patents Assigned to VeriSilicon Microelectronics
  • Patent number: 11599334
    Abstract: A device for performing multiply/accumulate operations processes values in first and second buffers and having a first width using a computational pipeline with a second width, such as half the first width. A sequencer processes combinations of portions (high-high, low-low, high-low, low-high) of the values in the first and second buffers using a multiply/accumulate circuit and adds the accumulated result of each combination of portions to a group accumulator. Adding to the group accumulator may be preceded by left shifting the accumulated result (the first width for the high-high combination and the second width for the low-high and high-low combination).
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: March 7, 2023
    Assignees: VeriSilicon Microelectronics, VeriSilicon Holdings Co., Ltd.
    Inventors: Mankit Lo, Meng Yue, Jin Zhang