Patents Assigned to VeriSilicon Microelectronics (Nanjing) Co., Ltd.
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Patent number: 11783513Abstract: The present disclosure provides a vector graphics data processing method, system, medium, and vector graphics processing device. The method includes the following operations: building a vector primitive path intersection data structure (PIDS) based on coordinates of path intersections (PIs); when a new PI is generated, comparing information of the new PI to information of existing PIs corresponding to an X coordinate or Y coordinate of the new PI; and storing the information of the new PI at a corresponding position in the PIDS corresponding to the X coordinate or Y coordinate of the new PI based on a result of the comparing. Only effective PI data are saved, thereby reducing memory footprint and memory bandwidth, and improving vector graphics processing performance.Type: GrantFiled: July 19, 2021Date of Patent: October 10, 2023Assignees: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd., VeriSilicon Microelectronics (Nanjing) Co., Ltd.Inventors: Mike M Cai, Yi Zhang, Yijun Li, Kui Qin
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Patent number: 11693820Abstract: The present disclosure provides a cooperative access method, system, and architecture of an external storage.Type: GrantFiled: December 2, 2019Date of Patent: July 4, 2023Assignees: VeriSilicon Microelectronics (Chengdu) Co., Ltd., VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd., VeriSilicon Microelectronics (Nanjing) Co., Ltd.Inventor: Yongliang Li
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Patent number: 11557090Abstract: The present disclosure provides a tessellation data processing method, system, medium and vector graphics processing device. The method includes: constructing a data structure including a content table and information tables in memory; when a vector line generated by tessellation intersects an horizontal/vertical line to obtain a new intersection, reading an address and number of Xnodes or Ynodes of an information table in the content table corresponding to a row/column corresponding to the Y/X coordinate of the intersection; according to the address of the information table and the number of X/Ynodes of the information table, reading corresponding X/Ynodes from the memory; comparing information of the intersection with the X/Ynodes, and updating the X/Ynodes in the information table, or adding an X/Ynode to the information table at a position corresponding to the Y/X coordinates.Type: GrantFiled: July 19, 2021Date of Patent: January 17, 2023Assignees: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd., VeriSilicon Microelectronics (Nanjing) Co., Ltd.Inventors: Cheng Chi, Jiangbo Li, Mike M Cai
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Patent number: 11557091Abstract: The present disclosure provides a tessellation data processing method, system, media, and vector graphics processing device. The method includes: according to specified coordinates of intersections, creating different levels of cache tables, wherein the intersections result from vector lines generated by tessellation intersecting lines parallel to an x-axis or y-axis; storing in a content table addresses of information tables in memory, storing in a lowest level cache table an address of the content table in the memory, and storing an address of the lowest level cache table in the memory in a cache table one level higher than the lowest level cache table. The tessellation data processing method, system, media, and vector graphics processing device of the present disclosure store effective data in multi-level lookup tables based on coordinates of intersections, effectively reduce memory footprint, support multi-channel tessellation processing, and enhance the performance of vector graphics rendering.Type: GrantFiled: July 19, 2021Date of Patent: January 17, 2023Assignees: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd., VeriSilicon Microelectronics (Nanjing) Co., Ltd.Inventors: Cheng Chi, Jiangbo Li, Mike M Cai
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Publication number: 20220342474Abstract: The present disclosure provides a method and system for controlling peak power consumption, which dynamically controls frequency by monitoring the load in real-time, thereby reducing the power consumption, and providing sufficient computing performance while controlling peak power consumption. The method and system for controlling peak power consumption of the present disclosure monitor the load in real-time, and reduce power consumption by dynamically and intelligently controlling the operating frequency, to achieve a balance between performance and power consumption, such that the chip works at the highest frequency when the peak power consumption does not exceed the load threshold, thereby effectively improving the work efficiency while achieving the power consumption control.Type: ApplicationFiled: December 2, 2019Publication date: October 27, 2022Applicants: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd., VeriSilicon Microelectronics (Nanjing) Co., Ltd.Inventor: Huiming ZHANG
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Patent number: 11455781Abstract: The present disclosure provides a data reading/writing method and system for in 3D image processing, a storage medium and a terminal. The method includes the following steps: dividing a 3D image horizontally based on the vertical sliding technology, the 3D image is divided into at least two subimages, a processing data of each subimage is stored in a circular buffer, after the subimage is processed, an overlapping portion data required by next subimage is retained in the circular buffer; dividing a multi-layer network of an image processing algorithm into at least two segments, the data between adjacent layers in each segment only interact through buffer, not through DDR.Type: GrantFiled: September 25, 2019Date of Patent: September 27, 2022Assignees: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd., VeriSilicon Microelectronics (Nanjing) Co., Ltd.Inventors: Zhonghao Cui, Mankit Lo, Ke Zhang, Huiming Zhang
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Publication number: 20220058838Abstract: The present disclosure provides a vector graphics data processing method, system, medium, and vector graphics processing device. The method includes the following operations: building a vector primitive path intersection data structure (PIDS) based on coordinates of path intersections (PIs); when a new PI is generated, comparing information of the new PI to information of existing PIs corresponding to an X coordinate or Y coordinate of the new PI; and storing the information of the new PI at a corresponding position in the PIDS corresponding to the X coordinate or Y coordinate of the new PI based on a result of the comparing. Only effective PI data are saved, thereby reducing memory footprint and memory bandwidth, and improving vector graphics processing performance.Type: ApplicationFiled: July 19, 2021Publication date: February 24, 2022Applicants: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd., VeriSilicon Microelectronics (Nanjing) Co., Ltd.Inventors: Mike M CAI, Yi ZHANG, Yijun LI, Kui QIN
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Publication number: 20220058867Abstract: The present disclosure provides a tessellation data processing method, system, media, and vector graphics processing device. The method includes: according to specified coordinates of intersections, creating different levels of cache tables, wherein the intersections result from vector lines generated by tessellation intersecting lines parallel to an x-axis or y-axis; storing in a content table addresses of information tables in memory, storing in a lowest level cache table an address of the content table in the memory, and storing an address of the lowest level cache table in the memory in a cache table one level higher than the lowest level cache table. The tessellation data processing method, system, media, and vector graphics processing device of the present disclosure store effective data in multi-level lookup tables based on coordinates of intersections, effectively reduce memory footprint, support multi-channel tessellation processing, and enhance the performance of vector graphics rendering.Type: ApplicationFiled: July 19, 2021Publication date: February 24, 2022Applicants: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd., VeriSilicon Microelectronics (Nanjing) Co., Ltd.Inventors: Cheng CHI, Jiangbo LI, Mike M CAI
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Publication number: 20220028165Abstract: The present disclosure provides a tessellation data processing method, system, medium and vector graphics processing device. The method includes: constructing a data structure including a content table and information tables in memory; when a vector line generated by tessellation intersects an horizontal/vertical line to obtain a new intersection, reading an address and number of Xnodes or Ynodes of an information table in the content table corresponding to a row/column corresponding to the Y/X coordinate of the intersection; according to the address of the information table and the number of X/Ynodes of the information table, reading corresponding X/Ynodes from the memory; comparing information of the intersection with the X/Ynodes, and updating the X/Ynodes in the information table, or adding an X/Ynode to the information table at a position corresponding to the Y/X coordinates.Type: ApplicationFiled: July 19, 2021Publication date: January 27, 2022Applicants: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd., VeriSilicon Microelectronics (Nanjing) Co., Ltd.Inventors: Cheng Chi, Jiangbo Li, Mike M Cai
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Publication number: 20220004522Abstract: The present disclosure provides a cooperative access method, system, and architecture of an external storage.Type: ApplicationFiled: December 2, 2019Publication date: January 6, 2022Applicants: VeriSilicon Microelectronics (Chengdu) Co., Ltd., VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd., VeriSilicon Microelectronics (Nanjing) Co., Ltd.Inventor: Yongliang LI
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Publication number: 20210295607Abstract: The present disclosure provides a data reading/writing method and system for in 3D image processing, a storage medium and a terminal. The method includes the following steps: dividing a 3D image horizontally based on the vertical sliding technology, the 3D image is divided into at least two subimages, a processing data of each subimage is stored in a circular buffer, after the subimage is processed, an overlapping portion data required by next subimage is retained in the circular buffer; dividing a multi-layer network of an image processing algorithm into at least two segments, the data between adjacent layers in each segment only interact through buffer, not through DDR.Type: ApplicationFiled: September 25, 2019Publication date: September 23, 2021Applicants: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd., VeriSilicon Microelectronics (Nanjing) Co., Ltd.Inventors: Zhonghao CUI, Mankit LO, Ke ZHANG, Huiming ZHANG