Patents Assigned to VeriSilicon Microelectronics (Shanghai) Co., Ltd.
  • Patent number: 11159254
    Abstract: The present disclosure provides an automatic mismatch calibration circuit and method, and a radio frequency receiver system. The automatic mismatch calibration circuit includes: at least one direct current (DC) offset estimation and calibration module coupled to a rear end of a radio frequency (RF) receiver to estimate a DC offset of received signals transmitted in an I channel and a Q channel to obtain an I-channel-DC-component and a Q-channel-DC-component, and compensate the I-channel-DC-component and the Q-channel-DC-component to the received signals corresponding to the I channel and the Q channel to achieve DC offset calibration. The present disclosure solves the problem that the existing mismatch calibration circuit cannot meet the low power consumption requirements of the system.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: October 26, 2021
    Assignees: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd.
    Inventors: Tingwen Xiong, Yi Zeng, Tony Qian
  • Publication number: 20210295607
    Abstract: The present disclosure provides a data reading/writing method and system for in 3D image processing, a storage medium and a terminal. The method includes the following steps: dividing a 3D image horizontally based on the vertical sliding technology, the 3D image is divided into at least two subimages, a processing data of each subimage is stored in a circular buffer, after the subimage is processed, an overlapping portion data required by next subimage is retained in the circular buffer; dividing a multi-layer network of an image processing algorithm into at least two segments, the data between adjacent layers in each segment only interact through buffer, not through DDR.
    Type: Application
    Filed: September 25, 2019
    Publication date: September 23, 2021
    Applicants: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd., VeriSilicon Microelectronics (Nanjing) Co., Ltd.
    Inventors: Zhonghao CUI, Mankit LO, Ke ZHANG, Huiming ZHANG
  • Publication number: 20210281218
    Abstract: The present disclosure provides a mixing circuit with high harmonic suppression ratio, including: a multi-phase generation module, which receives a first input signal and generates eight first square wave signals with a phase difference of 45°; a quadrature phase generation module, which receives a second input signal and generates four second square wave signals with a phase difference of 90°; a harmonic suppression module, connected with an output end of the quadrature phase generation module to filter out higher order harmonic components in the second square wave signals; and a mixing module, connected with output ends of the multi-phase generation module and the harmonic suppression module to mix output signals of the multi-phase generation module and the harmonic suppression module. The mixing circuit with high harmonic suppression ratio adds a harmonic suppression module on the basis of multi-phase mixing, thereby improving the harmonic suppression ratio of the output signal.
    Type: Application
    Filed: September 30, 2020
    Publication date: September 9, 2021
    Applicants: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd.
    Inventors: Yu LI, Peng MA, Yi ZENG, Shenglei WANG, Tony QIAN
  • Patent number: 11057069
    Abstract: The present disclosure provides a radio frequency (RF) front-end of a low power consumption and fully automatic adjustable broadband receiver, including a low-noise amplification module, amplifying an broadband single-ended RF signal, and converting it into differential current signal; a local oscillator, generating a local oscillator signal; an quadrature mixer, quadraturely mixing the differential current signal and the local oscillator signal to generate intermediate frequency differential current signals; a transimpedance amplifier, converting the intermediate frequency differential current signal into an intermediate frequency differential voltage signal; an IIP2 calibration module, reducing the IIP2 effect of the RF front end; a received signal strength indicator module, sending the first amplification factor control signal and the differential mismatch control signal to the low noise amplification module, and sending the second amplification factor control signal to the transimpedance amplifier, thereb
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: July 6, 2021
    Assignees: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd.
    Inventor: Fanzhen Meng
  • Patent number: 11055903
    Abstract: The present disclosure provides an edge anti-aliasing graphic processing method, system, storage medium and apparatus. The method includes: obtaining four sampling points by double sampling a pixel horizontally and vertically and performing rasterization to the pixel, determining whether the four sampling points are covered by a triangle; performing a depth value test on the pixel, and determining whether the four sampling points of the pixel are all covered by the triangle; performing final color processing on the pixel, determining whether the four sampling points are covered by the triangle, if the four sampling points are all covered by the triangle, copying a color of the pixel center point to the four sampling points, if not all the four sampling points are covered by the triangle, mixing colors of the four sampling points of the pixel.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: July 6, 2021
    Assignees: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd.
    Inventors: Ping Wang, Yongjun Chen, Huiming Zhang, Mike Cai
  • Publication number: 20210143920
    Abstract: The present disclosure provides an automatic mismatch calibration circuit and method, and a radio frequency receiver system. The automatic mismatch calibration circuit includes: at least one direct current (DC) offset estimation and calibration module coupled to a rear end of a radio frequency (RF) receiver to estimate a DC offset of received signals transmitted in an I channel and a Q channel to obtain an I-channel-DC-component and a Q-channel-DC-component, and compensate the I-channel-DC-component and the Q-channel-DC-component to the received signals corresponding to the I channel and the Q channel to achieve DC offset calibration. The present disclosure solves the problem that the existing mismatch calibration circuit cannot meet the low power consumption requirements of the system.
    Type: Application
    Filed: September 30, 2020
    Publication date: May 13, 2021
    Applicants: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd.
    Inventors: Tingwen XIONG, Yi ZENG, Tony QIAN
  • Publication number: 20210075457
    Abstract: The present disclosure provides a radio frequency (RF) front-end of a low power consumption and fully automatic adjustable broadband receiver, including a low-noise amplification module, amplifying an broadband single-ended RF signal, and converting it into differential current signal; a local oscillator, generating a local oscillator signal; an quadrature mixer, quadraturely mixing the differential current signal and the local oscillator signal to generate intermediate frequency differential current signals; a transimpedance amplifier, converting the intermediate frequency differential current signal into an intermediate frequency differential voltage signal; an IIP2 calibration module, reducing the IIP2 effect of the RF front end; a received signal strength indicator module, sending the first amplification factor control signal and the differential mismatch control signal to the low noise amplification module, and sending the second amplification factor control signal to the transimpedance amplifier, thereb
    Type: Application
    Filed: August 4, 2020
    Publication date: March 11, 2021
    Applicants: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd.
    Inventor: Fanzhen MENG
  • Patent number: 10862485
    Abstract: The present disclosure is directed to a method of utilizing a lookup table (LUT) where the index to the LUT does not need to be modified or changed in cases where the LUT is larger than a single register or larger than a set of available registers. In another embodiment, a processor instruction is disclosed that can take in one or more indices to a LUT and return the lookup results, without modifying the indices, when the LUT is larger than the available register data element space. In another embodiment, a SIMD processor system is disclosed that can implement a processor instruction to utilize a LUT that is larger than the available register data element space without needing to modify the parameterized index when a different subset of the LUT is swapped into the available registers.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: December 8, 2020
    Assignees: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd.
    Inventor: Steve Jarboe
  • Publication number: 20200160592
    Abstract: The present disclosure provides an edge anti-aliasing graphic processing method, system, storage medium and apparatus. The method includes: obtaining four sampling points by double sampling a pixel horizontally and vertically and performing rasterization to the pixel, determining whether the four sampling points are covered by a triangle; performing a depth value test on the pixel, and determining whether the four sampling points of the pixel are all covered by the triangle; performing final color processing on the pixel, determining whether the four sampling points are covered by the triangle, if the four sampling points are all covered by the triangle, copying a color of the pixel center point to the four sampling points, if not all the four sampling points are covered by the triangle, mixing colors of the four sampling points of the pixel.
    Type: Application
    Filed: February 10, 2020
    Publication date: May 21, 2020
    Applicants: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd.
    Inventors: Ping WANG, Yongjun CHEN, Huiming ZHANG, Mike Cai
  • Patent number: 10571989
    Abstract: A data collection system includes one or more input sensing devices and a data collection device. The data collection device includes data collection circuitry that is continuously activated to capture measurement data samples from the one or more input sensing devices and locally store the measurement data samples. The data collection device also includes a digital processor that is coupled to the data collection circuitry and is activated to locally perform a sample analysis of the measurement data samples, wherein the sample analysis is a regular analysis of routine measurement data samples when the measurement data samples are without a triggering event, and wherein the sample analysis is an event analysis when the measurement data samples include a triggering event. A data collection integrated circuit and a measurement data sample collection method are also included.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: February 25, 2020
    Assignees: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd.
    Inventors: Seshagiri Prasad Kalluri, Vijayanand Angarai, Adam Christopher Krolnik, Venkata Krishna Vemireddy