Abstract: An electronic device includes: a base layer; a first layer located at least partially over the base layer; a second layer located at least partially over the first layer; a first metal layer located at least partially over the second layer, wherein one or more signal outputs of the electronic device are formed in the first metal layer; and a second metal layer located at least partially over the first metal layer, wherein one or more gate connection is formed in the second metal layer, wherein removing a portion of the second metal layer disrupts at least one gate connection and deactivates the device.

Abstract: It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that allows for the design of chips that are difficult to reverse engineer using modern teardown techniques. The disclosed device uses devices having the same geometry but different voltage levels to create different logic devices. Alternatively, the disclosed uses devices having different geometries and the same operating characteristics. Also disclosed is a method of designing a chip using these devices.

Abstract: It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that allows for the design of chips that are difficult to reverse engineer using modern teardown techniques. The disclosed device uses devices having the same geometry but different voltage levels to create different logic devices. Alternatively, the disclosed uses devices having different geometries and the same operating characteristics. Also disclosed is a method of designing a chip using these devices.

Abstract: A ROM circuit includes a first N channel transistor having an output and having device geometry and device characteristics adapted to bias the output at a predetermined level when a P channel circuit is connected to the first N channel transistor; a pass transistor connected between the output and a data bus, the pass transistor connected to a word line, the word line adapted to turn ON the pass transistor when the word line is asserted; and the P channel circuit connected to the data bus and adapted to provide leakage current to charge a gate in the first N channel transistor when pass transistor is turned ON.

Abstract: Method and system for routing EPP requests over a network are provided. A routing system includes multiple frontend service interfaces, one or more gateways, a management server, and a backend service platform that provides multiple application services. The frontend service interfaces are addressable using virtual IP addresses (“VIP”) and can be provided by the gateways. The routing system defines a many-to-many mapping between the frontend service interfaces and a set of services provided by the backend service platform. A requestor can send a request over EPP to a targeted service interface to access one or more backend services, by sending the request to a target IP or domain name that corresponds to a VIP associated with the targeted service interface. Using the many-to-many mapping and the VIP of the targeted service interface, the routing system can identify backend services sought by the request and provide the requestor with access to the backend services.