Abstract: The multi-user server technology allows multiple host stations to configure, load, and execute multiple jobs in a reconfigurable hardware unit for emulation purposes, simulation acceleration purposes, and a combination of emulation and simulation in a concurrent manner. The reconfigurable hardware unit includes a plurality of hardware resources (e.g., FPGA chips on slot module boards) for modeling at least a portion of one or more user design. The server includes a bus arbiter for deciding which one of the host stations will be coupled to the hardware resources via the bus multiplexer. The plurality of hardware resources includes slot modules, which includes one or more boards of FPGA chips. An arbitration decision is made to assign a particular slot(s) to a particular host. A host and its respective assigned slot(s) can communicate with each other while other hosts and their respective assigned slot(s) communicate with each other.

Abstract: A method and apparatus for improved race detection and expression is disclosed. The race detection method and apparatus disclosed herein detects races statically by analyzing the circuits, which are usually written in a hardware description language (HDL), such as VHDL or Verilog. Compared with known simulation approaches, the inventive method and apparatus has at least the following advantages: no test vectors are required; all potential races can be detected; and in simulator approaches, if the right test vectors are not provided, then the races cannot be found (the invention avoids this last constraint).

Abstract: A system and method for automated design verification. A test bench stimulates a simulated design with test vectors. A coverage analysis tool monitors output data from the simulated design and identifies portions of the simulated design that remain to be tested. A test generator produces and sends test vectors to the test bench which exercise (i.e., test) the portions of the simulated design that the coverage analysis tool has indicated still remain untested. In the method, a first step executes a simulated design on a test bench. A second step interprets the simulated design as if this design were a state diagram composed of a set of basic blocks interconnected by transition arcs. A third step generates test vectors to exercise some of the basic blocks and transition arcs. A fourth step reports the basic blocks and transition arcs which have not been tested. A fifth step generates a new set of test vectors to exercise the as yet untested basic blocks and transition arcs.

Abstract: A method and apparatus for improved race detection and expression is disclosed. The race detection method and apparatus disclosed herein detects races statically by analyzing the circuits, which are usually written in a hardware description language (HDL), such as VHDL or Verilog. Compared with known simulation approaches, the inventive method and apparatus has at least the following advantages: no test vectors are required; all potential races can be detected; and in simulator approaches, if the right test vectors are not provided, then the races cannot be found (the invention avoids this last constraint).

Abstract: An electronic circuit design environmentally constrained test generation system provides a corrector mechanism that filters the input signals to the design under verification (DUV) and ensures that inputs signals to the DUV are within the given environmental constraints that describe the limitations on the permissible inputs to the DUV. Both combinational and temporal constraints can be handled by the corrector, which consists of a new element, a mapper, and an observer. The mapper looks at the observer's state and external test sequence input value and changes non-compliant test sequence input to the DUV to place the DUV in a legal state if the input would place it on a track to an illegal state, thereby constraining the inputs to the normal expected operating environment of the DUV. An illegal state is a state from which the violation of at least one constraint is unavoidable. A feedback loop from the DUV to the observer may be implemented using constraints that rely upon the DUV's state.

Abstract: To identify a finite state machine and verify a circuit design, the invention identifies, in a design description, a set of constructs, a construct in the set of constructs, and an object in the construct. It next identifies a first subset of constructs in the set of constructs which can control a change of a value of the object, and then identifies a second subset of constructs whose values can be changed directly or indirectly by the object. The identifying and storing steps are repeated for all objects in the construct and for all constructs in the set of constructs. A finite state machine is identified by searching for a first object which controls a change of a value of a second object and whose value is also changed directly or indirectly by the second object. This method of identifying finite state machine elements in a design description is used by a test generator which then generates test vectors for exercising the finite state machine elements on a test bench.

Abstract: A system and method for automated design verification. A test bench stimulates a simulated design with test vectors. A coverage analysis tool monitors output data from the simulated design and identifies portions of the simulated design that remain to be tested. A test generator produces and sends test vectors to the test bench which exercise (i.e., test) the portions of the simulated design that the coverage analysis tool has indicated still remain untested. In the method, a first step executes a simulated design on a test bench. A second step interprets the simulated design as if this design were a state diagram composed of a set of basic blocks interconnected by transition arcs. A third step generates test vectors to exercise some of the basic blocks and transition arcs. A fourth step reports the basic blocks and transition arcs which have not been tested. A fifth step generates a new set of test vectors to exercise the as yet untested basic blocks and transition arcs.