Abstract: Inductive proof can be an improvement to bounded verification. Forward and backward inductive proof methods are disclosed, which can improve the process of verifying properties of circuit designs.

Abstract: An equivalence checking method provides first and second logic functions. Don't care gates are inserted for don't care conditions in the first and second logic functions. The insertion of the don't care gates creates a first intermediate circuit and a second intermediate circuit. All 3DC gates of the first intermediate circuit are propagated and merged into a single 3DC gate when 3DC gates and SDC gates coexist in either of the first and second intermediate circuits. All 3DC gates of the second intermediate circuit are propagated and merged into a single 3DC gate when 3DC gates and SDC gates coexist in either of the first and second intermediate circuits. First and second circuits are produced in response to propagating and merging the 3DC gates. A combinational equivalence check is then performed of the first circuit to the second circuit under different equivalence relations.

Abstract: Integrated proof flow methods and apparatuses are discussed. Integrated proof flow refers to attempting both formal verification and nonformal verification. A coverage metric can be changed by both attempting formal verification and by attempting nonformal verification. Some embodiments of the present invention provide proof flow methods that integrate verification and nonformal verification (e.g., bounded verification, multi-point proof, and/or vector-based simulation) to prove one or more properties in a circuit design.

Abstract: A method for supporting non-assignable signals during formal verification of a circuit design includes providing a propagation logic for non-assignable signals and identifying a relevant cone in a circuit design, where the relevant cone determined by a property to verify. The method also includes designating one or more signals in the circuit design as non-assignable signals and propagating within the relevant cone any of the designated one or more non-assignable signals using the propagation logic for non-assignable signals. The method further includes ensuring, if a counter-example disproving the property exists, that the counter-example does not comprise any of the one or more designated non-assignable signals. A formal verification system that supports the designation of non-assignable signals comprises a non-assignable signal truth table and a proof engine. The non-assignable signal truth table specifies a propagation logic for non-assignable signals.