Abstract: Stacked die assemblies are electrically connected to connection sites on any support, without electrical connection to any interposed substrate or leadframe, and without solder.

Abstract: A die has interconnect pads on an interconnect side near an interconnect edge and has at least a portion of the interconnect side covered by a conformal dielectric coating, in which an interconnect trace over the dielectric coating forms a high interface angle with the surface of the dielectric coating. Because the traces have a high interface angle, a tendency for the interconnect materials to “bleed” laterally is mitigated and contact or overlap of adjacent traces is avoided. The interconnect trace includes a curable electrically conductive interconnect material; that is, it includes a material that can be applied in a flowable form, and thereafter cured or allowed to cure to form the conductive traces. Also, a method includes, prior to forming the traces, subjecting the surface of the conformal dielectric coating with a CF4 plasma treatment.

Abstract: Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.

Abstract: Stacked die assemblies are electrically connected to connection sites on any support, without electrical connection to any interposed substrate or leadframe, and without solder.

Abstract: A flat leadless package includes at least one die mounted onto a leadframe and electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, an assembly includes stacked leadless packages electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, a package module includes an assembly of stacked leadless packages mounted on a support and electrically connected to circuitry in the support using an electrically conductive polymer or an electrically conductive ink.

Abstract: Methods are disclosed for improving electrical interconnection in stacked die assemblies, and stacked die assemblies are disclosed having structural features formed by the methods. The resulting stacked die assemblies are characterized by having reduced electrical interconnect failure.

Abstract: Additive processes are employed for electrically insulating selected surface regions on a stack of die; and methods for electrically interconnecting die in a stack of die, include additive processes for electrically insulating selected surface regions of the die. Regions that are not insulated according to the invention are available for electrical connection using electrically conductive material applied in flowable form to make electrically conductive traces.

Abstract: An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board).

Abstract: A method for flip-chip interconnection includes applying a dielectric film onto the active side of the die, or onto the die mount side of the substrate, or both onto the die and onto the substrate; then orienting and aligning the die in relation to the substrate, and moving the die toward the substrate so that interconnect contact is made; then treating the assembly (for example by heating or by heating and pressing) to complete the electrical connections and to cause the film to soften and to adhere. Also, a method for flip-chip assembly includes completing electrical connection of the flip-chip interconnects on a die with bond pads on a substrate and thereafter exposing the assembly to a CVD process to fill the headspace between the die and the substrate with a dielectric material. Also, a flip-chip assembly is made by the method. Also, a die or a substrate is prepared for flip-chip interconnection by applying a dielectric film on a surface thereof.

Abstract: According to the invention, die shift is reduced or substantially eliminated, by cutting the wafer in two stages. In some embodiments a first wafer cutting procedure is carried out prior to thinning the wafer to the prescribed die thickness; and in other embodiments the wafer is thinned to the prescribed die thickness prior to carrying out a first wafer cutting procedure. The first wafer cutting procedure includes cutting along a first set of streets to a depth greater than the prescribed die thickness and optionally along a second set of streets to a depth less than the die thickness. The result of the first cutting procedure is an array of strips or blocks of die, each including a plurality of connected die, that are less subject to shift than are individual singulated die. In a second wafer cutting procedure the die are singulated by cutting through along the second set of streets.

Abstract: An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board).

Abstract: In die stack assembly configurations successive die in the stack are offset at a die edge at which die pads are situated, and the die are interconnected by electrically conductive traces. In some embodiments the electrically conductive traces are formed of an electrically conductive polymer. An electrically insulative conformal coating is provided having openings at die pads that are electrically connected.

Abstract: A flat leadless package includes at least one die mounted onto a leadframe and electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, an assembly includes stacked leadless packages electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, a package module includes an assembly of stacked leadless packages mounted on a support and electrically connected to circuitry in the support using an electrically conductive polymer or an electrically conductive ink.

Abstract: According to the invention, die shift is reduced or substantially eliminated, by cutting the wafer in two stages. In some embodiments a first wafer cutting procedure is carried out prior to thinning the wafer to the prescribed die thickness; and in other embodiments the wafer is thinned to the prescribed die thickness prior to carrying out a first wafer cutting procedure. The first wafer cutting procedure includes cutting along a first set of streets to a depth greater than the prescribed die thickness and optionally along a second set of streets to a depth less than the die thickness. The result of the first cutting procedure is an array of strips or blocks of die, each including a plurality of connected die, that are less subject to shift than are individual singulated die. In a second wafer cutting procedure the die are singulated by cutting through along the second set of streets.

Abstract: A die (or of a stack of die) is mounted over and elevated above a support, and is electrically connected to circuitry in the support. Pillars of electrically conductive material are formed on a set of bond pads at a mount side of the support, and the elevated die (or at least one die in the elevated stack of die) is electrically connected to the support, by traces of an electrically conductive material contacting interconnect pads on the die to the pillars, and through the pillars to the support. Also, tiered offset stacked die assemblies in a zig-zag configuration, in which the interconnect edges of a first (lower) tier face in a first direction, and the interconnect edges of a second (upper) tier, stacked over the first tier, face in a second direction, different from the first direction, are electrically connected to a support.

Abstract: A flat leadless package includes at least one die mounted onto a leadframe and electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, an assembly includes stacked leadless packages electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, a package module includes an assembly of stacked leadless packages mounted on a support and electrically connected to circuitry in the support using an electrically conductive polymer or an electrically conductive ink.

Abstract: An interconnect terminal is formed on a semiconductor die by applying an electrically conductive material in an aerosol form, for example by aerosol jet printing. Also, an electrical interconnect between stacked die, or between a die and circuitry in an underlying support such as a package substrate, is formed by applying an electrically conductive material in an aerosol form, in contact with pads on the die or on the die and the substrate, and passing between the respective pads. In some embodiments a fillet is formed at the inside corner formed by an interconnect sidewall of the die and a surface inboard from pads on an underlying feature (underlying die or support); and the electrically conductive material passes over a surface of the fillet.

Abstract: A sensor die in a sensor device includes a conformal dielectric coating over at least a die sidewall adjacent an interconnect edge and, in some devices, a conformal dielectric coating over at least part of the active area of the front side of the die. The sensor die can be connected to circuitry in a support by an electrically conductive material that is applicable in a flowable form, such as a curable electrically conductive polymer, which is applied onto or adjacent the dielectric coating on the die sidewall, and which is cured to complete connection between interconnect pads on the die and exposed sites on the support circuitry. In some devices, a coating over the active area of the sensor die provides mechanical and chemical protection for underlying structures in and on the die. In an image sensor device, for example, the coating over the image sensor array on the die is substantially optically transparent.

Abstract: Semiconductor die are typically manufactured as a large group of integrated circuit die imaged through photolithographic means on a semiconductor wafer or slice made of silicon. After manufacture, the silicon wafer is thinned, usually by mechanical means, and the wafer is cut, usually with a diamond saw, to singulate the individual die. The resulting individual integrated circuit has six exposed surfaces. The top surface of the die includes the circuitry images and any passivation layers that have been added to the top layer during wafer fabrication. The present invention describes a method for protecting and insulating all six surfaces of the die to reduce breakage, provide electrical insulation for these layers, and to provide physical surfaces that can be used for bonding one semiconductor die to another for the purpose of stacking die in an interconnected module or component.

Abstract: An image sensor die includes a conformal dielectric coating over at least a die sidewall adjacent an interconnect edge and, in some embodiments, a conformal dielectric coating over the image array area of the front side of the die. The die can be connected to circuitry in a support by an electrically conductive material that is applicable in a flowable form, such as a curable electrically conductive polymer, which is applied onto or adjacent the dielectric coating on the die sidewall, and which is cured to complete connection between interconnect pads on the die and exposed sites on the support circuitry. The coating over the image array area, at least, is substantially transparent to visible light, and provides mechanical and chemical protection for underlying structures in and on the image sensor.