Abstract: Embodiments of the present disclosure may relate to a voltage reference generator comprising: a local heater structured to generate continuous controlled temperature and uniform thermal profile, at multiple points further comprising a Bipolar Junction, Transistors, and a heating element. Embodiments may additionally include temperature compensated resistances adopted to generate constant temperature compensated voltage reference current using an operational amplifier, a transistor, and two or more resistors, positive and negative. The embodiments may further include, current mirrors comprising a plurality of MOS transistors configured to mirror current flowing in the PMOS transistor.

Abstract: In accordance with the present invention a system and method for calibration of the current steering DAC is elaborated which helps to reduce design complexity and reduce silicon area required in the design. Present invention is utilising a clocked comparator and plurality of switch transistors 405,305 and AUX DAC in conjunction with digital estimator and digital compensator blocks to estimate the errors in the current sources 406 and compensate the errors using same AUX DAC during normal operation mode.

Abstract: The present invention discloses a method of calibrating time interleaved analog to digital converter comprising: sampling a common input signal, said sampling is performed by an array of sub analog to digital converters, each generating individual digital analog equivalent outputs with sampling time errors, said digital outputs are fed to sampling time error estimation circuitry to calculate a digital output proportional to sampling time error between two consecutive channels, without any restriction on input signal or ADC channel design, said timing skew estimator circuitry composed of generating a delayed output of one of the two consecutive ADC channels, channel first and channel second and subtracting the said delayed output with digital output of the said second channel and producing the first subtracted output and output of said second channel subtracted with said first channel output delayed by sampling delay between the two consecutive channels and producing the second subtracted delayed output, absol

Abstract: A multilevel analog to digital converter (ADC) is composed of noise shaping filter and multi-level quantizer, where said quantizer is made from an array of comparators, each coupled with one reference level, the said quantizer is coupled with a thermometric digital to analog converters (DAC) in the feedback path, the said DAC output is compared with ADC input and error is fed to noise shaping filter, said reference levels of each quantizer is generated from a digital to analog converter coupled with a digital quantizer reference controller and said digital quantizer reference controller is randomly changing the reference levels in a way that quantizer coupled DAC elements are indirectly randomised to improve the overall linearity and noise performance of the converter.

Abstract: The present invention discloses a method of calibrating time interleaved analog to digital converter comprising: sampling a common input signal, said sampling is performed by an array of sub analog to digital converters, each generating individual digital analog equivalent outputs with sampling time errors, said digital outputs are fed to sampling time error estimation circuitry to calculate a digital output proportional to sampling time error between two consecutive channels, without any restriction on input signal or ADC channel design, said timing skew estimator circuitry composed of generating a delayed output of one of the two consecutive ADC channels, channel first and channel second and subtracting the said delayed output with digital output of the said second channel and producing the first subtracted output and output of said second channel subtracted with said first channel output delayed by sampling delay between the two consecutive channels and producing the second subtracted delayed output, absol

Abstract: In accordance with the present invention a system and method for calibration of the current steering DAC is elaborated which helps to reduce design complexity and reduce silicon area required in the design. Present invention is utilising a clocked comparator and plurality of switch transistors 405,305 and AUX DAC in conjunction with digital estimator and digital compensator blocks to estimate the errors in the current sources 406 and compensate the errors using same AUX DAC during normal operation mode.