Abstract: The invention provides a new linked structure for a buffer controller and management method thereof. The allocation and release actions of buffer memory can be more effectively processed when the buffer controller processes data packets. The linked structure enables the link node of the first buffer register to point to the last buffer register. The link node of the last buffer register points to the second buffer register. Each of the link nodes of the rest buffers points to the next buffer register in order until the last buffer register. This structure can effectively release the buffer registers in the used linked list to a free list.

Abstract: The present invention provides a method for receiving an instruction for varying the bus frequency from a current bus frequency to a new frequency. The method may include storing a group of parameters corresponding to a second frequency, disabling a link connected to the host bus at a first frequency while the host bus is being operated with parameters corresponding to the first frequency, updating the parameters for operating the host bus with the group of parameters, and enabling the link at the second bus frequency to operate the host bus with the group of parameters.

Abstract: A patch apparatus includes fuse banks, one or more configuration fuse banks, and an array controller. The fuse banks are configured to store associated patch records that are employed to patch microcode or machine state circuits in the microprocessor or to store associated control data entities that are employed to program control circuits in the microprocessor. The configuration fuse banks are encoded to indicate whether each of the plurality of fuse banks is programmed with one of the associated patch records or with one of the associated control data entities. The array controller reads the fuse banks, and provides the associated patch records to a patch loader or the associated control data entities to control circuits in the microprocessor. The patch loader provides patches corresponding to the associated patch records, as prescribed, to designated target patch mechanisms in the microprocessor.

Abstract: A patch mechanism in a microprocessor is provided. The patch mechanism includes an expansion RAM and a patch loader. The expansion RAM stores a plurality of patches, where a first one or more of the plurality of patches are to be executed by the microprocessor in place of a corresponding one or more micro instructions which are stored in a microcode ROM, and where a second one or more of the plurality of patches are employed to patch a corresponding one or more machine states in the microprocessor. The patch loader is coupled to the expansion RAM, and is configured to retrieve the plurality of patches from a source external to the microprocessor, and is configured to load the plurality of patches into the expansion RAM.

Abstract: A microcode patch apparatus including a patch array, a mux, and a RAM. The patch array receives a microcode ROM address and determines that the microcode ROM address matches one of a plurality of entries within the patch array. The patch array outputs a corresponding branch instruction and asserts a hit signal. The branch instruction prescribes a microcode branch target address. The mux receives the branch instruction from the patch array and a micro instruction corresponding to the microcode ROM address from a microcode ROM. The mux provides the micro instruction or the corresponding branch instruction to an instruction register based upon the state of the hit signal. The RAM stores a plurality of patch instructions that are to be executed in place of the micro instruction. The first one of the plurality of patch instructions is stored at a location in the RAM corresponding to the microcode branch target address.

Abstract: A microcode patch apparatus including a patch array, a mux, and a RAM. The patch array receives a microcode ROM address and determines that the microcode ROM address matches one of a plurality of entries within the patch array. The patch array outputs a corresponding branch instruction and asserts a hit signal. The branch instruction prescribes a microcode branch target address. The mux receives the branch instruction from the patch array and a micro instruction corresponding to the microcode ROM address from a microcode ROM. The mux provides the micro instruction or the corresponding branch instruction to an instruction register based upon the state of the hit signal. The RAM stores a plurality of patch instructions that are to be executed in place of the micro instruction. The first one of the plurality of patch instructions is stored at a location in the RAM corresponding to the microcode branch target address.

Abstract: An apparatus for performing microcode patches that is both fast and flexible. In one embodiment, an apparatus for performing a real-time microcode patch is provided. The apparatus includes a patch array and a mux. The patch array receives a microcode ROM address and determines that the microcode ROM address matches one of a plurality of entries within the patch array. When the microcode ROM address matches, the patch array outputs a corresponding patch instruction and to assert a hit signal. The mux receives the patch instruction from the patch array and a micro instruction corresponding to the microcode ROM address from a microcode ROM. The mux provides the micro instruction or the corresponding patch instruction to an instruction register based upon the state of the hit signal.

Abstract: A microcode patch expansion mechanism includes a patch RAM, an expansion RAM, and a controller. The patch RAM stores a first plurality of patch instructions. The first plurality is to be executed by the microprocessor in place of one or more micro instructions which are stored in a microcode ROM. The expansion RAM stores a second plurality of patch instructions. The number of the second plurality is greater than the number of the first plurality. The second plurality is to be executed by the microprocessor in place of a second one or more micro instructions which are stored in the microcode ROM. The controller executes an EXPRAM micro instruction directing that one or more of the second plurality of patch instructions be loaded into the patch RAM, and loads the one or more of the second plurality of patch instructions into the patch RAM.

Abstract: A patch apparatus in a microprocessor is provided. The patch apparatus includes a plurality of fuse banks and an array controller. The plurality of fuse banks is configured to store associated patch records that are employed to patch microcode or circuits in the microprocessor. The array controller is coupled to the plurality of fuse banks, and is configured to read the associated patch records, and is configured to provide the associated patch records to a patch loader, where the patch loader provides patches corresponding to the associated patch records, as prescribed, to designated target patch mechanisms in the microprocessor. The patch loader provides the patches to the designated target patch mechanisms following transition of a microprocessor reset signal and prior to execution of instructions stored in a BIOS ROM.

Abstract: In a wireless local area network media access controller (MAC) disposed in a first node of a wireless local area network, a method is performed to synchronize the clock of the first node with the clock of a second node in the wireless local area network. When a request signal is asserted from the first node to the second node, a responsive signal packet containing a time stamp is asserted from the second node to the first node in response to the request signal. Then, the MAC tags a local time value to the responsive signal packet at the first node, and operates the time stamp and the local time value according to a control program to obtain a difference T, which is stored in a register of the MAC. Afterwards, at least one of the clocks of the first and the second nodes is adjusted to synchronize the clocks of the first and the second nodes according to the difference T.

Abstract: A data packet transmission method for use in a network switch is disclosed. The network switch includes a plurality of connection ports for tranceiving a data packet therefrom, a tag substitution rule table defining a tag substitution rule, a VLAN reference table defining the correlation of a tagging rule with a VLAN information of the data packet, a multicast reference table defining the relationship of a multicast port mask with a multicasting information of the data packet, and a tag determination device. The tag determination device transmits the data packet to destination ports according to the multicast port mask, determines the VLAN tag(s) to be affixed to the data packet for the destination ports according to the tag substitution rule, and optionally removes the VLAN tag for the destination ports according to the tagging rule.

Abstract: A frequency synthesizer with a single PLL and multiple SSB mixers is presented. The frequency synthesizer includes a single PLL outputting a reference signal that is fed to a plurality of dividers coupled in sequence. The outputs from the dividers are mixed by the SSB mixers to produce signals with different frequencies. These signals with different frequencies can be selected through use of multiple selectors.