Abstract: A light emitting diode (LED) device and packaging with enhance heat conduction. An LED in a wafer level processing (WLP) package is disclosed using vias in the silicon to route the electrical connections to the LED backside and a dedicated hole in the silicon with a direct heat conduction route from the LED to the printed circuit board. Certain layers act to promote mechanical, electrical, thermal, or optical characteristics of the device. The device avoids or ameliorates heat dissipation problems found in conventional LED devices. Some embodiments include a plurality of optically permissive layers, including an optically permissive cover substrate comprising phosphors and/or quantum dots.
Abstract: Wafer level packaging of LED devices is accomplished using a bottom wafer that includes one or more vias. A passivation layer is placed over the top surface of the bottom wafer including the surface of the vias. Metal pads are placed on the top surface of the passivation layer and extend to the bottom of the vias. Bond pads are then associated with the metal pads and ultimately used in attaching an LED device bottom wafer assembly. An encapsulation layer is applied and in contact with the LED device and a top wafer is attached to the encapsulation layer. The thickness of the bottom wafer is reduced, removing the lower portion to expose the metal pads at the bottom of the vias. An isolation layer is applied to the bottom wafer and holes are formed in the isolation layer to expose the metal pads. Electroplated structures are in contact with the isolation layer and in contact with the exposed metal pads.
Abstract: Wafer level packaged semiconductor device with enhanced heat dissipation properties. The semiconductor device includes a top and a bottom face and at least one metal pad is positioned on the top and the bottom faces. A top cover is affixed to the top face of the semiconductor device and a bottom cover is affixed to the bottom face of the semiconductor device. Vias extend through the top and bottom covers and an electroplated metal layer extends from an external face of the covers, through the visas to the metal pads on the semiconductor device.
Abstract: Aspects of the invention include an electronic device comprising a first contact point; a metal pad disposed to provide electrical connection to the first contact point; a substrate comprising a first face and a second face opposing the first face of the substrate, the first face of the substrate adjacent a face of the electronic device; and a VIA passing through the substrate from the second face of the substrate to the metal pad, the VIA exhibiting: a pass through extending through the substrate from the first face to the second face; a metal layer disposed within the pass through arranged to provide electrical connectivity to the metal pad from an area adjacent the second face of the substrate; and an electrically insulating first passivation layer disposed between the metal layer and the substrate arranged to provide electrical insulation between the substrate and the metal layer.