Abstract: Systems and methods of manufacturing printed circuit boards using blind and internal micro vias to couple subassemblies. An embodiment of the invention provides a method of manufacturing a printed circuit including attaching a plurality of metal layer carriers to form a first subassembly including at least one copper foil pad on a first surface, applying an encapsulation material onto the first surface of the first subassembly, curing the encapsulation material and the first subassembly; applying a lamination adhesive to a surface of the cured encapsulation material, forming at least one via in the lamination adhesive and the cured encapsulation material to expose the at least one copper foil pad, attaching a plurality of metal layer carriers to form a second subassembly, and attaching the first subassembly and the second subassembly.
Type:
Grant
Filed:
October 28, 2013
Date of Patent:
August 15, 2017
Assignee:
Viasystems Technologies Corp., L.L.C.
Inventors:
Rajesh Kumar, Monte P. Dreyer, Michael J. Taylor
Abstract: A method of manufacturing at least a portion of a printed circuit board. The method includes: applying a lamination adhesive on a first plural-layer substrate that includes a plurality of circuit layers with at least one first metal pad on a first side of the first plural-layer substrate; applying a protective film on the lamination adhesive; forming at least one via into the lamination adhesive to expose the at least one metal pad on the first side of the first plural-layer substrate; filling at least one conductive paste into the at least one via formed in the lamination adhesive; removing the protective film to expose the lamination adhesive on the first plural-layer substrate; and attaching the first plural-layer substrate with a second plural-layer substrate that includes a plurality of circuit layers with at least one second metal pad on a second side of the second plural-layer substrate.
Type:
Grant
Filed:
October 20, 2014
Date of Patent:
November 1, 2016
Assignee:
Viasystems Technologies Corp., L.L.C.
Inventors:
Raj Kumar, Monte P. Dreyer, Michael J. Taylor
Abstract: Systems and methods for reducing overhang on electroplated surfaces of printed circuit boards are described. One such method includes applying a first resist layer on a substrate having a first copper layer, applying a first image to the first resist layer, developing the first resist layer in accordance with the first image, applying a second copper layer on the first copper layer, electroplating a first metallic layer on the second copper layer, removing the first resist layer, etching a portion of the first copper layer, removing the first metallic layer, depositing a third copper layer on a surface of the assembly, applying a second resist layer on the third copper layer, applying a second image to the second resist layer, developing the second resist layer in accordance with the second image, electroplating a preselected metal layer on the third copper layer, removing the second resist layer, and etching a portion of the third copper layer.
Type:
Grant
Filed:
June 16, 2011
Date of Patent:
April 28, 2015
Assignee:
Viasystems Technologies Corp. L.L.C.
Inventors:
Rajwant S. Sidhu, Ruben A. Zepeda, Carlos A. Lopez
Abstract: Aspects of the present invention are directed to providing a printed circuit board including a top conductive layer; a bottom conductive layer; a plurality of electronic components arranged on at least one of the top conductive layer or the bottom conductive layer; a heater layer interposed between the top conductive layer and the bottom conductive layer and configured to generate and transfer heat to at least one of the electronic components.
Abstract: A method of manufacturing at least a portion of a printed circuit board. The method includes: applying a lamination adhesive on a first plural-layer substrate that includes a plurality of circuit layers with at least one first metal pad on a first side of the first plural-layer substrate; applying a protective film on the lamination adhesive; forming at least one via into the lamination adhesive to expose the at least one metal pad on the first side of the first plural-layer substrate; filling at least one conductive paste into the at least one via formed in the lamination adhesive; removing the protective film to expose the lamination adhesive on the first plural-layer substrate; and attaching the first plural-layer substrate with a second plural-layer substrate that includes a plurality of circuit layers with at least one second metal pad on a second side of the second plural-layer substrate.
Type:
Grant
Filed:
November 2, 2010
Date of Patent:
February 10, 2015
Assignee:
Viasystems Technologies Corp., L.L.C.
Inventors:
Raj Kumar, Monte Dreyer, Michael J. Taylor