Abstract: A programmable interconnect structure to couple a first wire segment to a second wire segment of an integrated circuit comprising: a pass-gate to electrically couple the first wire segment to the second wire segment fabricated on a substrate layer; and a configuration circuit including at least one memory element to control said pass-gate fabricated substantially above said substrate layer, wherein changing data stored in the memory element provides a programmable method to achieve one of: isolate said first wire segment from sad second wire segment; and couple said first wire segment to said second wire segment.

Abstract: A new Static Random Access Memory (SRAM) cell using Thin Film Transistors (TFT) is disclosed. In a first embodiment, an SRAM cell comprises a strong inverter and a strong access device constructed on a semiconductor substrate layer, and a weak inverter and a weak access device constructed in a semiconductor thin film layer located vertically above the strong devices. The strong devices are used in the data read and write paths, and the weak devices are used for latch feed-back and sector data erase. This first embodiment is used for high density and high speed memory applications. In a second embodiment, an SRAM cell comprises thin film inverters and thin film access devices constructed in a semiconductor thin film layer located substantially above logic transistors. The TFT SRAM cell is buried above the logic gates of an Integrated Circuit to consume no extra Silicon real estate. This second embodiment is used for slow access and Look-Up-Tables type memory applications.

Abstract: A three-dimensional semiconductor device with two selectable manufacturing configurations includes a first module layer having a plurality of circuit blocks; and a second module layer formed substantially above the first module layer, wherein in a first selectable configuration a plurality of memory circuits are formed to store instructions to control a portion of the circuit blocks, and wherein in a second selectable configuration a predetermined conductive pattern is formed in lieu of the memory circuit to control substantially the same portion of the circuit blocks.