Abstract: Timing exact design conversions from an original field programmable device to an application specific device is disclosed. In a first aspect, a design conversion from a field programmable gate array (FPGA) to an application specific integrated circuit (ASIC) comprises a user configurable element in the FPGA replaced by a mask configurable element in the ASIC. In a second aspect, an FPGA design conversion to an ASIC comprises converting a user configurable memory bit pattern generated by a software tool to program the programmable content of the FPGA to a hard-wired metal pattern for the ASIC.

Abstract: A highly economical alterable ASIC implements partitioned segments of an ASIC design in a smaller Silicon foot-print, each segment utilizing the entire IC. The device is able to switch quickly between the multiple segments with global control signals, without incurring long delays to reconfigure configuration memory. The alterable ASIC comprises programmable logic blocks and a configuration circuit with multiple sets of configuration memory, each set programmed to hold an optimized segment. Either random access memory (RAM) or mask configured read only memory (ROM) store the partitioned segments.