Patents Assigned to Victory Company of Japan, Ltd.
  • Patent number: 5894332
    Abstract: A television receiver is disclosed which is designed to display two types of input picture signals, for example, an NTSC signal and a VGA signal on at least two display areas of one image screen simultaneously. The television receiver includes an auxiliary coil and a switching circuit. The auxiliary coil is operable in first and second operation modes. The first operation mode is such that an electron beam is scanned in sequence along the scanning lines to reproduce the VGA signal having a horizontal scanning frequency of substantially twice that of the NTSC input signal, while the second operation mode is such that the scanning line intervals are controlled so as to scan the electron beam two times along the same scanning line to reproduce the consecutive two of line signals of the frequency-converted NTSC signal which are formed by the same portion of the NTSC input signal.
    Type: Grant
    Filed: September 23, 1996
    Date of Patent: April 13, 1999
    Assignee: Victory Company of Japan, Ltd.
    Inventor: Nobuyoshi Yamagishi
  • Patent number: 5848239
    Abstract: A variable-speed communication and reproduction system consists of a server and a client device, and comprises a variable-speed data supplier for supplying a requested data set at a play speed specified by the user. The variable-speed data supplier includes the server. A control data communication system and a time-series data communication system are also included in the data supplier, which connect the server and the client. The communication and reproduction system further comprises a variable-speed reproducer for reproducing the data set supplied from the variable-speed data supplier at the specified play speed by adjusting the pitch of audio and the video frequencies, and a play speed setter responsive to the specified play speed for setting the specified play speed to the variable-speed data supplier and the variable-speed reproducer.
    Type: Grant
    Filed: September 30, 1996
    Date of Patent: December 8, 1998
    Assignee: Victory Company of Japan, Ltd.
    Inventor: Ichiro Ando
  • Patent number: 4931743
    Abstract: A noise reduction circuit comprises a first circuit for extracting a relatively high frequency component of an input signal and amplitude-limiting a component of said extracted high frequency component exceeding a predetermined level, a second circuit for delaying said input signal such as a video signal by a predetermined time, and a third circuit for adding outputs of said first and second circuits and outputting an added result as an output of said noise reduction circuit.
    Type: Grant
    Filed: July 10, 1987
    Date of Patent: June 5, 1990
    Assignee: Victory Company of Japan, Ltd.
    Inventors: Hisatoshi Fukuda, Hisashige Fujiwara