Abstract: A bandgap apparatus includes an error amplifier; a bandgap core including 2 BJT devices and core resistors for proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) current generations; a reference resistor for reference voltage generation; an NMOS current mirror having NMOS devices; a PMOS current mirror having PMOS devices; and 4 switches for controlling operation in a high-power mode or a low-power mode, wherein the high-power mode consumes more power than the low-power mode, wherein the error amplifier is switched on and the NMOS current mirror is switched off in the high-power mode, or the error amplifier is switched off and the NMOS current mirror is switched on in the low-power mode.

Abstract: A voltage regulation loop includes a voltage reference generation block that includes a bandgap voltage reference circuit; a linear voltage regulator block that includes a first and second linear voltage regulators, wherein the first linear voltage regulator provides a first regulated power supply to the bandgap voltage reference circuit in the voltage reference generation block, and the second linear voltage regulator provides a second regulated power supply to a load; and a soft startup circuit connected between the voltage reference generation block and the linear voltage regulator block, wherein a selector functions with a control block to output a selected voltage reference to pass to the soft startup circuit, wherein the soft startup circuit smooths the selected voltage reference and produces a smoothed voltage reference to pass to the linear voltage regulator block to prevent overshoots at startup.

Abstract: An apparatus includes a poly current generator circuit, which includes a fractional bandgap circuit, or a bandgap voltage reference circuit and a current reference generator, an adaptive bias current generator, a frequency generator to generate an output clock signal having a select frequency, wherein the frequency generator includes a current starved ring oscillator that comprises n identical cascaded stages connected in a shape of a ring, wherein an output of the nth cascaded stage is fed back as an input of the first cascaded stage, wherein n is an odd number greater than or equal to 3; and clock buffers configured to buffer the output clock signal generated by the frequency generator for distribution.

Abstract: A current reference circuit with one or more current mirror devices having dynamic body biasing includes a voltage-to-current converter circuit having a feedback loop that includes an operational amplifier, an NMOS device, and a resistor to generate a reference current; a current mirror circuit, including one or more current mirror devices with source degeneration, to produce one or more output currents that are copies of the reference current; and a body-biasing stage including an active N-well to dynamically set a body-biasing voltage for the one or more current mirror devices.

Abstract: A dual loop regulated switched-capacitor converter circuit includes a switched capacitor array that includes a plurality of switches and capacitors; a digital controller for controlling the switched capacitor array; a pulse modulator connected to the digital controller; a clock generator connected to the digital controller; a first comparator connected to the pulse modulator; and a feedback network connected to the first comparator.

Abstract: An apparatus and methods for timing mismatch in a power amplifier includes a segmented PA with two-path timing mismatch calibration to improve ACLR performance over different signal transitions, process, voltage and temperature (PVT) variations and device aging; a fast and efficient algorithm for measuring and calibrating the delay of two paths (signal path and control path); a signal magnitude variation detection circuit, such as flash ADC, with improved comparator's performance for RF signal processing and minimum delay. A method for choosing the threshold voltage of the magnitude variation detection circuit, according to status of the signals and orthogonal frequency-division multiplexing (OFDM) related standards; other critical blocks.

Abstract: A voltage regulation loop includes a voltage reference generation block that includes a bandgap voltage reference circuit; a linear voltage regulator block that includes a first and second linear voltage regulators, wherein the first linear voltage regulator provides a first regulated power supply to the bandgap voltage reference circuit in the voltage reference generation block, and the second linear voltage regulator provides a second regulated power supply to a load; and a soft startup circuit connected between the voltage reference generation block and the linear voltage regulator block, wherein a selector functions with a control block to output a selected voltage reference to pass to the soft startup circuit, wherein the soft startup circuit smooths the selected voltage reference and produces a smoothed voltage reference to pass to the linear voltage regulator block to prevent overshoots at startup.

Abstract: A system for processing of signals with poles that are low in frequency includes a switched capacitor circuit that includes two switches connected to an input and an output of a switching capacitor (Cs), respectively, in an alternating manner at a selected switching frequency (fSW); and a filter capacitor connected between an input and the switched capacitor circuit. The filter capacitor and the switched capacitor circuit together function as a filter, thereby a pole frequency depending on a ratio of capacitance of the switching capacitor (Cs) and the filter capacitor, instead of an RC product.

Abstract: A bandgap reference circuit includes a circuit for high-order temperature curvature compensation; and a circuit for low output impedance and current drive capability, wherein an output voltage of the bandgap reference circuit can be independently adjusted to be either above or below a silicon bandgap voltage without impacting temperature curvature.

Abstract: A voltage regulator includes a load detection controller for detecting whether an output capacitor is present at an output of the voltage regulator; a digital controller for selecting a functional state of the voltage regulator based on a signal from the load detection controller; a first feedback loop for regulation when the output capacitor is not present; a second feedback loop for regulation when the capacitance output capacitor is present; and a first pass transistor shared by the load detection controller, the first feedback loop, and the second feedback loop, wherein the first pass transistor is configured to work with the first or second feedback loop selected for regulation based on the functional state of the voltage regulator.

Abstract: A load detection circuit includes a variable current source circuit having a first input connected to a power supply, a second input, and a first output connected to an output load; a switched capacitor circuit having a third input connected to an external voltage reference signal, a fourth input connected to the first output of the variable current source, a fifth input connected to ground, a sixth input, and a second output; a comparator having a seventh input connected to the second output of the switched capacitor circuit, an eighth input connected to the first output of the variable current source, and a third output; an edge detector having a ninth input connected to the third output of the comparator, and a fourth output; and a digital controller having a fifth output connected to the variable current source and a sixth output connected to the switched capacitor circuit.

Abstract: A bandgap reference circuit includes a circuit for high-order temperature curvature compensation; and a circuit for low output impedance and current drive capability, wherein an output voltage of the bandgap reference circuit can be independently adjusted to be either above or below a silicon bandgap voltage without impacting temperature curvature.

Abstract: A band-gap reference circuit includes a band-gap voltage reference core to provide a reference voltage; a low impedance block; three capacitors; two transmission gates to connect and disconnect the capacitors; and two digital control blocks. The three capacitors includes an output capacitor connected at an output of the low impedance block to ground; a small capacitor connected to an output of the band-gap voltage reference core; and a large capacitor connected to the two transmission gates. The band-gap voltage reference core includes an operational amplifier, wherein an output of the operational amplifier connects to an input of the low impedance block and the small capacitor, wherein the small capacitor is also connected to ground; and a combination of bipolar junction transistors, MOS-FET, resistors, capacitors, or FinFET devices that provides a reference voltage.

Abstract: A power-on reset (POR) circuit with an auxiliary control circuit and an enhanced resistor ladder for brownouts circuit detectors in low power applications includes a power-up detector circuit for detecting power supply ramp-up while charging; a brownout detector circuit for sensing power supply falling down; a set-reset (SR) latch to generate a power-on-reset (POR) signal; a start-up network; and an internal band-gap voltage reference circuit, wherein the internal band-gap voltage reference circuit is configured to be started by the start-up network to serve as a reference for the power-up detector circuit.

Abstract: A silicon based (e.g., SiGe, CMOS, or BiCMOS) transmitter includes an algorithm that strategically segment and pre-distort the input signal according to its power; a reconfigurable power amplifier (PA) having a plurality of PA sections, wherein the plurality of PA sections comprise discrete weighted transistor arrays that are digitally turned OFF or ON according to a magnitude of an input signal; an impedance matching network equipped with a common-mode feedback (CMFB) mechanism configured to reduce common-mode glitches at an output of the PA due to ON/OFF manipulations of the PA segments; and a 1:N transformer, which comprises a capacitive matching engine and a power detector, disposed between the impedance matching network and the reconfigurable linear PA.

Abstract: A low-dropout (LDO) voltage regulator includes an adaptive bias source for generating a bulk-bias signal to a pass device in the LDO voltage regulator, wherein the adaptive bias source generates the bulk-bias signal based on a signal obtained at an output of the LDO voltage regulator. The signal includes a current signal, which is proportional to a current at the output of the LDO voltage regulator, and/or a feedback signal from a feedback path connected between the adaptive bias source and the output of the LDO voltage regulator for sensing negative and/or positive spikes.

Abstract: A novel low power enable circuit is less sensitive to power supply variations while consuming less than 50 nA of supply current. The enable circuit includes a voltage clamp circuit which limits the supply level for a first inverter. The clamp circuit having a first input connected to a supply, a second input connected to chip enable, and a first output.

Abstract: An adaptive negative impedance system for improving power supply rejection (PSR) of a voltage regulator (VR) includes a variable negative impedance circuit with a control input; and a signal adjustment block (SAB), wherein a negative impedance value of the variable negative impedance circuit is dependent on a voltage regulator output current, and wherein the variable negative impedance circuit is a variable negative capacitance circuit and/or a variable negative resistance circuit, and the negative impedance value is a negative capacitance value and/or a negative resistance value.

Abstract: An automatically reconfigurable Buck-Boost DC-DC converter having an input supply and an output voltage includes a linear regulator (LDO) for Buck configuration; a switched-capacitor DC-DC converter; a capacitor and switch array, and a gain selector to switch between the linear regulator (LDO) when an output DC level is higher than an input DC level (Buck configuration) and the switched-capacitor DC-DC converter when the output DC level is lower than the input DC level (Boost configuration).

Abstract: A load detection circuit includes a variable current source circuit having a first input connected to a power supply, a second input, and a first output connected to an output load; a switched capacitor circuit having a third input connected to an external voltage reference signal, a fourth input connected to the first output of the variable current source, a fifth input connected to ground, a sixth input, and a second output; a comparator having a seventh input connected to the second output of the switched capacitor circuit, an eighth input connected to the first output of the variable current source, and a third output; an edge detector having a ninth input connected to the third output of the comparator, and a fourth output; and a digital controller having a fifth output connected to the variable current source and a sixth output connected to the switched capacitor circuit.