Abstract: A circuit design tool which includes (1) separating structural and functional aspects of components, so as to specify the desired functional behaviour of the component, leaving the actual gate-level design of the component to the design tool; (2) translating a model of the desired logical behaviour of a circuit into a regularized set of functional components to achieve that desired behaviour; (3) verifying structural equivalence between pairs of components; (4) a method for bit-reversing the signal flow in a component; (5) a method for performing arithmetic operations backwards from a natural order; (6) an architecture for a multiplier which is faster and more compact than known multipliers; and (7) a method of translating a logic equation into a netlist of connected logic gates.

Abstract: The invention provides a method and system for automated circuit design case management. A computer system maintains a set of cases for circuit design, in which each case comprises a set of files, in one or more directories, representing the circuit design. For example, each case may comprise a circuit schematic, a symbolic representation for a circuit element, a set of timing information, or a wiring diagram. The system provides a set of tools for automated management, manipulation, and verification of cases. The system provides a technique by which a designer or other user may create a case in which the program maintains assertions regarding the state of the circuit, the mode of operation, or the purpose of analysis for that case. The system provides a technique by which a designer or other user may modify a first case, or create a second case modeled on the first case, in which a first subset of the files for each case is invariant and a second subset of the files differ between the two cases.

Abstract: A circuit design tool which includes an architecture for a multiplier which is faster and more compact than known multipliers through the use of Wallace trees, the elimination of Dadda nodes along the critical paths, the placement of half-adders at an initial pat of the Wallace tree, the replacement of low-order terminating adders with ripple-carry adders, and the replacement of high-order terminating adders with carry-select adders.

Abstract: A system and method for resolving three-state busses while generating a compact vector set which will detect as many stuck-at faults as possible. Two passes are made through the circuit design. In the first pass, all three-state busses in the design are satisfied at the same time to eliminate conflicts on all of the busses and the ordered pairs of inputs for resolving the bus are saved. In the second pass, a primary fault is targeted and a sequence is generated to detect the fault and is saved for later reference. Then secondary faults are targeted to find input sets that will detect the secondary faults and if such inputs will also satisfy all of the three-state busses, the primary inputs for the secondary fault are saved.

Abstract: A system and method for programmatically adding pads and ports and altering design logic at the terminals of electronic circuit designs is provided. In a preferred embodiment the system and method are implemented within a system that partitions arbitrary designs but the system and method may be used by itself to add terminal logic. Patterns and connections of removable logic of the internal circuitry can be specified by a user or by system default settings stored in an external file.