Abstract: A partitioned source line architecture for reducing leakage and power in a ROM. In one embodiment, a ROM includes of a plurality of storage cells organized as an array having M rows and N columns. Each column is associated with a precharged source line that is partitioned into a plurality of source line segments based on the number of row banks of the array. A plurality of local source line decoder circuits corresponding to the row banks are provided for decoding a selected source line segment based on the column address as well as a Bank Select signal generated from the row address of a particular cell. Local pull-down circuitry is provided with each bank for deactivating the selected source line segment upon commencing a memory access operation.

Abstract: A method and apparatus for testing a memory at speed. A test and repair wrapper integrated with a memory instance is operable to receive test information scanned in from a built-in self-test and repair (BISTR) processor. Logic circuitry associated with the test and repair wrapper is operable to generate address, data and command signals based on the scanned test information, wherein the signals are used for effectuating one or more tests with respect to the memory instance.

Abstract: A hierarchically organized, compilable semiconductor memory circuit having multiple levels with simultaneous access and cache loading. A first level memory portion and at least a next level memory portion are provided as part of the semiconductor memory circuit, wherein the memory portions are associated with separate Data In (DIN) and Data Out (DOUT) buffer blocks for effectuating data operations. DIN buffer blocks of the first level and intermediate levels, if any, are provided with multiplexing circuitry that is selectively actuatable for providing data accessed in the next level memory portion to Local Data In (LDIN) driver circuitry, whereby the accessed data is simultaneously loaded into the first and intermediate levels. Accordingly, extra clock cycles are saved from cache loading of the data used for subsequent memory operations.

Abstract: A static memory cell having reduced susceptibility to soft error events, wherein data storage nodes are hardened by way of junction isolation. The memory cell is comprised of a pair of cross-coupled inverters. A first inverter is formed with a first N-channel Metal Oxide Semiconductor (NMOS) device and a first P-channel MOS (PMOS) device, with a first isolation device disposed therebetween. A second inverter is cross-coupled to the first inverter to form a pair of data storage nodes therein. The second inverter is also provided with a second isolation device disposed between its pair of NMOS and PMOS devices. A first data storage node is formed at a coupling between the first PMOS device and the first isolation device and a second data storage node is formed at a coupling between the second PMOS device and the second isolation device.

Abstract: A memory characterization system and method using a hierarchically-stitched netlist generation technique. A plurality of leaf cells forming a memory instance are generated based on a minimum area required to encompass an optimal number of memory strap points relating to global signals that span the memory instance. Input and output pins are defined for each tile with respect to the global signals in both horizontal and vertical directions. A parametric dataset is obtained for each tile using an extractor (wherein the memory instance is in post-layout condition) or a pre-layout wire-delay estimator. The parametric netlist for the entire memory instance is assembled by coupling the individual parametric datasets using the input and output pins of the tiles with respect to the global signals.

Abstract: A semiconductor memory with multiple timing loops for optimizing memory access operations. A clock generator circuit is provided for generating an internal memory clock based on an external clock or an input signal transition supplied to the memory device. The internal memory clock is operable to provide a timing reference with respect to a memory access operation based on a plurality of address signals. A timing loop selector is operable to select a particular timing loop responsive to at least one access margin signal. A shutdown circuit generates an access shutdown signal based on the selected timing loop that is optimized for a memory device of particular size, speed, etc.

Abstract: A compilable ROM architecture with enhanced performance characteristics, i.e., increased speed and lowered power consumption, wherein a plurality of memory locations are organized into one or more I/O blocks, each having a select number of bitlines. Each memory location is addressable by a row address and a column address. The data is stored in the ROM using a scrambled addressing scheme wherein a portion of the row and column addresses is interchanged in order to minimize bitline loading of the binary 0's.

Abstract: A system and method for redundancy implementation in an integrated semiconductor device having at least one memory instance that includes a prime memory array and a redundant portion. A fuse box register is provided outside the memory macro cell associated with the memory instance. The fuse box register is operable to store location information pertaining to a faulty portion in the prime memory array. A redundancy scan storage element in the memory instance is operable to receive the location information from the fuse box register, which location information is used for replacing at least a part of the faulty portion in the prime memory array with at least a part of the redundant portion.

Abstract: Circuitry and method for effectuating low power read operations in a memory circuit, e.g., a memory instance having a banked architecture. When a memory read cycle is initiated with respect to a particular memory cell in a selected bank based on a plurality of address signals, a specific wordline associated with the memory cell is driven high. Upon waiting until the bitline coupled thereto reach a predetermined sense level, the wordline is shut off based on a reference memory cell structure, which wordline thereby stops driving the bitline. Subsequently, after waiting for a select time, the sense amplifier senses the data stored in the particular memory cell based a charge distribution between its internal node(s) and the bitline after the selected wordline is deactivated.

Abstract: Circuitry and associated method for resetting a memory storage cell without a dedicated write cycle therefor. Preferably, the storage cell is provided as part of an age_array employed for monitoring the usage of a Content Addressable Memory (CAM). When a match between search data and contents of a particular location of the CAM is found, a Match signal is generated to set a memory storage cell (referred to as an age_cell) corresponding to the particular CAM location. When the age_array is read, the wordline associated with the age_cell is driven high. Upon developing a voltage separation between the data and data bar nodes of the age_cell, a sense amp senses the data value on the corresponding bit and bit bar lines coupled thereto. A suitable data out signal is generated for outputting the sensed data. Also, a reset control signal is generated to indicate that the read operation is substantially complete with respect to that age_cell.

Abstract: A circuit for selectively erasing a semiconductor memory instance on a per I/O basis. The circuit is provided as a tilable architectural element in a memory compiler for the semiconductor memory instance. A plurality of pass gates are disposed between global wordlines provided by the row decoder of the memory array and local wordlines that select memory bit cells in a particular I/O. One or more memory clear signals are used to decouple the local wordlines from the global wordlines and to connect them to a high voltage node, VDD. The I/O is cleared by placing a predetermined logic state (typically 0) on the bitline nodes of the I/O and selectively coupling the local wordlines to the VDD node.

Abstract: A compilable ROM architecture with enhanced performance characteristics, i.e., increased speed and lowered power consumption, wherein a plurality of memory locations are organized into one or more I/O blocks, each having a select number of bitlines. At least a portion of the data map in the ROM is manipulated so as to achieve a desired distribution of 0's and 1's such that the loading of 0's on the bitlines is reduced. In one exemplary embodiment, the data map is inverted per bitline, per I/O, or both. Output path circuitry is appropriately manipulated for accurate outputting of the original data. In another embodiment, the data is stored in the ROM using a scrambled addressing scheme wherein a portion of the row and column addresses is interchanged in order to minimize bitline loading of the binary 0's.

Abstract: A row and column accessible memory having a plurality of memory cells organized as an array of N rows and N columns with a built-in multiplex. A control logic block and decoder block are operable to effectuate either a row access operation for accessing a selected row or a column access operation for accessing a selected column based on a plurality of address signals supplied to the memory. Each memory cell is provided with a first pair of read and write ports for effectuating the row access operations (controlled through row read wordline select and row write wordline select signals, respectively) and a second pair of read and write ports for effectuating the column access operations (controlled through column read wordline select and column write wordline select signals, respectively). A single I/O block is utilized for sensing and data I/O operations, which requires less silicon area and avoids extra routing required in the conventional solutions.

Abstract: A semiconductor memory architecture for embedded memory instances having redundancy. A fuse box register is provided outside the memory macro associated with the memory instances. The memory instances are daisy-chained to the fuse box register containing a plurality of fuses used for storing fuse data associated with the defective rows and columns of main memory. During power-up or after blowing the fuses, the contents of the fuses (i.e., fuse data) are transferred to a plurality of volatile redundancy scan flip-flops. The fuse box is then deactivated to eliminate quiescent current through the fuses. The redundancy scan flip-flops, connected in a scan chain, are located inside the fuse box as well as the memory instances. During the shifting mode of operation, the fuse contents are scanned into individual flip-flops, organized as scan registers for row redundancy and column redundancy, of the memory instances.

Abstract: A reduced latency row selection circuit and method for selecting a wordline in a memory instance. Capacitance associated with row select path is de-coupled from capacitance associated with row de-select path such that both forward path delay and de-selection path delay may be optimized independently. Clock-to-wordline latency is reduced by a rapid six-stage structure that may be implemented using various logic gates. A row pre-decoder portion generates a decoded wordline clock (DXC) signal based on a row decode select clock (XC) signal and a portion of pre-decoded row address signals. The DXC signal is used by a row decoder portion for generating a wordline select (XWL) signal based on another portion of the address signals. Circuitry is provided for releasing the selected wordline in the memory upon receiving a wordline shutdown clock signal generated responsive to signals provided by dummy wordline and dummy read bitline structures disposed in the memory.

Abstract: A hierarchical sense amp and write driver (SA/WD) circuitry architecture for compilable high-density memory. A predetermined number of secondary, or regional, SA/WD blocks segment the main array associated with the memory instance in multiple banks. Each secondary SA/WD block is coupled to a tertiary, or global, SA/WD block via a global I/O line operating to effectuate data I/O on a per I/O basis with respect to the memory instance. A select number of primary SA/WD blocks per each secondary SA/WD block are specified, wherein the primary SA/WD blocks segment a memory bank associated with a particular secondary SA/WD block into a plurality of sub-banks. Each primary SA/WD block is coupled to a select secondary SA/WD block associated therewith via a common regional I/O line. A select number of memory cells per bitline segment for each of the memory sub-banks may be specified as part of compiling a memory instance for a particular application.

Abstract: Self-timed clock circuitry for use in a compilable memory instance using a common timing synchronization node. A plurality of memory banks are provided in the memory instance wherein each memory bank is independently selectable by a bank select (BS) signal generated by a global control circuit. A global timing circuit is provided to drive a common node signal on the common timing synchronization node to a high value upon application of an external master clock and a memory enable signal to the memory instance. The global timing circuit is operable to drive the common node signal high for a predetermined time period. A local driver circuit associated with a particular memory bank selected by a specific BS signal takes over control of driving the common node signal thereafter so as to maintain its high state. Upon completing the memory access operation, a reference signal within the particular memory bank is driven low.

Abstract: A full signal swing differential output path circuit for rapidly transferring a latched data value on a pair of complementary global data nodes (QT and QB) to a single-ended output of a compilable memory instance. At least one tri-statable sense amplifier is disposed between the complementary global data nodes which operates to sense a small differential voltage between a pair of complementary bitlines disposed in a bank of memory storage cells during an access operation associated therewith. A pair of precharge pull up devices are provided for precharging the complementary global data nodes QT and QB to a predetermined voltage, e.g., VDD. In a preferred embodiment, the precharge pull up devices preferably comprise P-channel MOS (PMOS) devices and are actuatable by an active low precharge signal. A first output of the sense amp is coupled to one of the complementary global data nodes (QB) and the complementary output (i.e.

Abstract: A divided wordline memory architecture for memory compilers wherein a main memory array is organized into a plurality of local memory arrays. A plurality of local wordline decoders are provided such that each local memory array is associated with a local wordline decoder for selecting local wordline segments. Main wordline signals are generated based on a first portion of wordline address signals in a main wordline decoder provided as an integrated centrally located decoder structure. A combination of Plane signals, Set signals, or both, which are generated in the integrated centrally located decoder structure, are provided to the local wordline decoder in conjunction with a portion of the main wordline signals for selecting a local wordline segment based on a select main wordline signal and one of a select Plane signal, a select Set signal, or a combination of both.

Abstract: The simultaneous read or simultaneous write memory array of the present invention includes a core array of memory units, control logic, a first port I/O, a first port shift register, first port word line generation logic, a second port I/O, a second port shift register, and a second port word line generation logic. The memory unit includes a pair of cells formed from two inverters as well as read and write transistors. The pair of memory cells preferably use the same bit lines for being read or written. Still more particularly, the novel design of the memory units combines the read and write bit lines into a single bit line such that there is a first, single bit line for reading from a first cell in the memory unit and writing to a second cell in the memory unit; and there is a second, single bit line for reading from the second cell in the memory unit and writing to the first cell in the memory unit.