Abstract: A method and apparatus for controlling memory access in a system where at least a first and a second processor each share a common memory. The first processor has a write buffer, in which it stores words prior to writing them in the common memory, and a cache for receiving words from the common memory. The common memory is mapped twice into the address space of the first processor so that, in a first mapping, the first processor accesses the common memory directly and in a second mapping, the cache is enabled. The common memory can therefore be directly accessed with the first processor and the second processor when they share data that is read from or written into the common memory. The cache is accessed with the first processor in the second mapping for reading and writing data local to the first processor. Information written into the write buffer is tagged and the tagged information is flushed into the shared memory before the shared memory can be accessed by the second processor.

Abstract: A system for connecting low-cost, simple peripherals to an ATM network is disclosed. A plurality of such devices is connected to a standard ATM switch in a ring configuration. A polling station, located remotely in the ATM network, periodically generates a token cell which is delivered to the switch and, thereafter, is transmitted onto the ring configuration. The devices transmit cells in response to the token cells by transmitting cells behind the token cell as they forward it around the ring. The resultant cell chain is received at the ATM switch, where the cells are then sent onto the ATM network using virtual circuits.