Patents Assigned to Virginia Semiconductor
  • Patent number: 6554687
    Abstract: A semiconductor wafer manufactured with a precise crystallographic-orientation alignment mark and a method of manufacturing. The method of manufacturing may include forcibly directing a carrier medium containing an abrasive material through a stencil to effect abrasive impact removal of a semiconductor surface in a defined machining area. The abrasive impact removal may be part of an automated machining process.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: April 29, 2003
    Assignee: Virginia Semiconductor, Inc.
    Inventors: Stephen H. Jones, Thomas G. Digges, Jr., Christopher Mark Mann, Grant H. Ancarrow
  • Patent number: 6428618
    Abstract: A method for forming a solid solution alloy crystal includes forming a solid solution alloy crystal having at least the same diameter as a seed crystal. The seed crystal is exposed to a liquid containing a desired concentration of an alloying element to dissolve a portion of the seed crystal. The solid solution alloy crystal is then formed from the liquid. The method allows a large diameter solid solution alloy crystal to be grown in a reduced time or a larger diameter solid solution alloy crystal to be grown in a known fixed total process time.
    Type: Grant
    Filed: February 9, 2001
    Date of Patent: August 6, 2002
    Assignee: Virginia Semiconductor, Inc.
    Inventors: Richard H. Deitch, Thomas G. Digges, Jr.
  • Patent number: 6390889
    Abstract: A holding strip is used to hold a semiconductor ingot during semiconductor wafer fabrication. The holding strip is formed from a semiconductor material, typically the same material used to form the ingot itself. The holding strip has a holding surface shaped to receive the ingot and at least one surface other than the holding surface, into which at least one notch is formed. The holding strip has a characteristic breaking strength that changes when a cut is formed through the holding surface and into the notch. In some embodiments, the notch has sides that are substantially parallel to each other, and in other embodiments, the notch has tapered sides. In alternative embodiments, the shape of the notch causes an abrupt change or a gradual change in the breaking strength of the holding strip as the cut penetrates into the notch. In either case, the notch can be shaped to cause a gradual change in breaking strength as the cut moves deeper into the notch.
    Type: Grant
    Filed: September 29, 1999
    Date of Patent: May 21, 2002
    Assignee: Virginia Semiconductor
    Inventors: A. Dempsey McGregor, Marshall P. Toombs, James E. Brooks, Benjamin J. Meadows
  • Patent number: 6367467
    Abstract: A holding unit is provided to support an ingot in a semiconductor wafer sawing machine, which minimizes the instability of a blade during a sawing process. The holding unit is formed from substantially the same material as an ingot resting thereon. The holding unit includes a top surface for receiving an ingot, a bottom surface, a pair of side walls, and a cavity formed in the holding unit. The cavity forms a plurality of break points in the holding unit. When contacted by the blade, the holding unit fractures at the break points to minimize the chipping of the wafer.
    Type: Grant
    Filed: June 18, 1999
    Date of Patent: April 9, 2002
    Assignee: Virginia Semiconductor
    Inventors: A. Dempsey McGregor, Marshall P. Toombs, James E. Brooks, Benjamin J. Meadows
  • Publication number: 20010004876
    Abstract: A method for forming a solid solution alloy crystal includes forming a solid solution alloy crystal having at least the same diameter as a seed crystal. The seed crystal is exposed to a liquid containing a desired concentration of an alloying element to dissolve a portion of the seed crystal. The solid solution alloy crystal is then formed from the liquid. The method allows a large diameter solid solution alloy crystal to be grown in a reduced time or a larger diameter solid solution alloy crystal to be grown in a known fixed total process time.
    Type: Application
    Filed: February 9, 2001
    Publication date: June 28, 2001
    Applicant: Virginia Semiconductor, Inc.
    Inventors: Richard H. Deitch, Thomas G. Digges
  • Patent number: 6251181
    Abstract: A method for forming a solid solution alloy crystal includes forming a solid solution alloy crystal having at least the same diameter as a seed crystal. The seed crystal is exposed to a liquid containing a desired concentration of an alloying element to dissolve a portion of the seed crystal. The solid solution alloy crystal is then formed from the liquid. The method allows a large diameter solid solution alloy crystal to be grown in a reduced time or a larger diameter solid solution alloy crystal to be grown in a known fixed total process time.
    Type: Grant
    Filed: June 18, 1999
    Date of Patent: June 26, 2001
    Assignee: Virginia Semiconductor
    Inventors: Richard H. Deitch, Thomas G. Digges, Jr.
  • Patent number: 6159285
    Abstract: A new ingot of a desired orientation formed from an original ingot of a different orientation by cutting the new ingot from within the original ingot. In one aspect, to form a <110> ingot from a <100> ingot, a {110} flat is formed on the <100> ingot. The flat is used as a reference for cutting the <100> ingot. The <100> ingot is cut into sections by cutting in a plane perpendicular to the <100> ingot's longitudinal axis and to the flat. A <110> ingot can be formed by grinding a section of the <100> ingot to form a new cylinder. The new cylinder has a longitudinal axis which is perpendicular to the <100> ingot's longitudinal axis and to the flat. The resulting cylinder is a <110> ingot.
    Type: Grant
    Filed: May 6, 1999
    Date of Patent: December 12, 2000
    Assignee: Virginia Semiconductor, Inc.
    Inventors: Marshall P. Toombs, Thomas G. Digges, Jr.
  • Patent number: 6080042
    Abstract: A wafer polishing apparatus includes one or more wafer carriers each containing one or more wafers mounted on both sides of the carrier. Upper and lower turntables having upper and lower polishing surfaces, rotate to polish the wafers attached to the carriers. Hence, wafers on the top of the carriers, and wafers on the bottom of the carriers are polished simultaneously. This configuration increases throughput; also, thermal deformations in the wafers are reduced, thus improving flatness.
    Type: Grant
    Filed: October 31, 1997
    Date of Patent: June 27, 2000
    Assignee: Virginia Semiconductor, Inc.
    Inventors: Anderson D. McGregor, Thomas G. Digges, Jr.
  • Patent number: 6057924
    Abstract: Techniques and systems for obtaining the thickness map of a partially transparent substrate in a nondestructive optical fashion. The thickness is determined by comparing the amount of absorption by the substrate to a calibrated amount obtained from a substrate standard with a known thickness that is formed of the same material. Digital signal processing operations are performed to reduce noise and to improve resolution of the thickness map.
    Type: Grant
    Filed: September 4, 1998
    Date of Patent: May 2, 2000
    Assignee: Virginia Semiconductor, Inc.
    Inventors: Robert A. Ross, Stephen H. Jones
  • Patent number: 5959731
    Abstract: Techniques and systems for measuring absolute thickness, the total thickness variation, and electric resistivity of a semiconductor substrate in a nondestructive optical fashion. Optical absorption is used to measure the absolute thickness of a semiconductor substrate with a light source and a photo transceiver. The thickness is determined by comparing the amount of absorption to a calibrated amount. Both the absolute thickness and total thickness variation of the substrate can be measured based on light absorption using an imaging device. The invention can be used to directly image and measure localized features formed on micro machined substrates. The resistivity of a substrate sample can also be measured by using an alternating electrical signal.
    Type: Grant
    Filed: October 29, 1997
    Date of Patent: September 28, 1999
    Assignee: Virginia Semiconductor, Inc.
    Inventor: Stephen H. Jones
  • Patent number: 5843832
    Abstract: A technique of bonding a thin wafer layer to a substrate. The wafer is blown dry using an inert gas to prevent it from being damaged, while still ensuring that it dries completely. The initial bonding is done by orienting crystallographic axes, and then allowing the wafers to adhere to one another slowly. The contact wave is prevented from spreading, by a divider between the two wafers. The wafers are allowed to adhere to one another slowly to form a bond. The bond is strengthened by annealing.
    Type: Grant
    Filed: March 1, 1995
    Date of Patent: December 1, 1998
    Assignee: Virginia Semiconductor, Inc.
    Inventors: Kenneth R. Farmer, Thomas G. Digges, Jr., N. Perry Cook
  • Patent number: 5754294
    Abstract: Techniques and systems for measuring absolute thickness, the total thickness variation, and electric resistivity of a semiconductor wafer in a nondestructive optical fashion. Optical absorption is used to measure the absolute thickness of a semiconductor wafer with a light source and a phototransceiver. The thickness is determined by comparing the amount of absorption to a calibrated amount. Coherent light interference is used to measure the total thickness variation of a substrate. Alternatively, both the absolute thickness and total thickness variation of the substrate can be measured based on light absorption using a CCD imaging device. The resistivity of a wafer sample can also be measured by using an alternating electrical signal.
    Type: Grant
    Filed: May 3, 1996
    Date of Patent: May 19, 1998
    Assignee: Virginia Semiconductor, Inc.
    Inventors: Stephen H. Jones, Carolyn DeMain, Robert A. Ross, David Abdallah, Thomas Digges