Patents Assigned to Virident Systems, Inc.
  • Patent number: 9135164
    Abstract: First data is received for storing in a first asymmetric memory device. A first writing phase is identified as a current writing phase. A first segment included in the first asymmetric memory device is identified as next segment available for writing data. The first data is written to the first segment. Information associated with the first segment is stored, along with information indicating that the first segment is written in the first writing phase. Second data is received for storing in the asymmetric memory. A second segment included in the first asymmetric memory device is identified as the next segment available for writing data. The second data is written to the second segment. Information associated with the second segment and the second memory block is stored along with information indicating that the second segment is written in the second writing phase.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 15, 2015
    Assignee: Virident Systems Inc.
    Inventors: Vijay Karamcheti, Shibabrata Mondal, Swamy Gowda
  • Patent number: 9122588
    Abstract: Some implementations provide a method for managing data in a storage system that includes a persistent storage device and a non-volatile random access memory (NVRAM) cache device. The method includes: accessing a direct mapping between a logical address associated with data stored on the persistent storage device and a physical address on the NVRAM cache device; receiving, from a host computing device coupled to the storage system, a request to access a particular unit of data stored on the persistent storage device; using the direct mapping as a basis between the logical address associated with the data stored on the persistent storage device and the physical address on the NVRAM cache device to determine whether the particular unit of data being requested is present on the NVRAM cache device.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 1, 2015
    Assignee: Virident Systems Inc.
    Inventors: Shibabrata Mondal, Vijay Karamcheti, Ankur Arora, Ajit Yagaty
  • Patent number: 9093150
    Abstract: A multi-chip packaged integrated circuit part for mounting to a printed circuit board of a memory module. The multi-chip packaged integrated circuit part comprises an integrated circuit package including a slave memory controller (SMC) die; and pairs of a spacer under the slave memory controller die, and a flash memory die under the spacer. In each pair, the flash memory die may be larger than the spacer so that an opening is provided into a perimeter of the flash memory die to allow electrical connections to be made. A plurality of conductors may be used to electrically couple the slave memory controller die and the flash memory die to one or more pads of a pin-out of the integrated circuit package.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: July 28, 2015
    Assignee: Virident Systems, Inc.
    Inventors: Vijay Karamcheti, Kumar Ganapathy
  • Patent number: 9021188
    Abstract: A first portion of an asymmetric memory is configured as temporary storage for application data units with sizes corresponding to a small memory block that is smaller than the size of a logical write unit associated with the asymmetric memory. A portion of the remaining asymmetric memory is configured as a reconciled storage for application data units with varying sizes. A first application data unit is received for writing to the asymmetric memory. Based on computing the size of the first application data unit as corresponding to the small memory block, the first application data unit is written to the temporary storage. Upon determining that a threshold is reached, a memory write operation is performed for writing the application data units from the temporary storage to the reconciled storage. The application data units written to the reconciled storage are removed from the temporary storage.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 28, 2015
    Assignee: Virident Systems Inc.
    Inventors: Vijay Karamcheti, Ashish Singhai, Shibabrata Mondal, Swamy Gowda
  • Patent number: 8996796
    Abstract: A first portion of an asymmetric memory is configured as temporary storage for application data units with sizes corresponding to a small memory block that is smaller than the size of a logical write unit associated with the asymmetric memory. A portion of the remaining asymmetric memory is configured as a reconciled storage for application data units with varying sizes. A first application data unit is received for writing to the asymmetric memory. Based on computing the size of the first application data unit as corresponding to the small memory block, the first application data unit is written to the temporary storage. Upon determining that a threshold is reached, a memory write operation is performed for writing the application data units from the temporary storage to the reconciled storage. The application data units written to the reconciled storage are removed from the temporary storage.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 31, 2015
    Assignee: Virident Systems Inc.
    Inventors: Vijay Karamcheti, Ashish Singhai, Shibabrata Mondal, Swamy Gowda
  • Patent number: 8972633
    Abstract: An apparatus includes a printed circuit board with a plurality of printed circuit board traces, a memory controller mounted on the printed circuit board coupled to one or more of the plurality of printed circuit board traces, a plurality of non-volatile type of memory integrated circuits coupled to the printed circuit board, and a plurality of support integrated circuits coupled between the memory controller and the plurality of non-volatile type of memory integrated circuits.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: March 3, 2015
    Assignee: Virident Systems, Inc.
    Inventors: Vijay Karamcheti, Kumar Ganapathy, Kenneth Alan Okin, Rajesh Parekh
  • Patent number: 8949555
    Abstract: In one embodiment of the invention, a memory system includes non-volatile-memory-devices (NVMDs) coupled to memory channels to share busses and a memory controller coupled to the memory channels in communication between the plurality of NVMDs. Each NVMD independently executes a read, write, or erase operation at a time. The memory controller includes channel schedulers to schedule control and data transfers associated with the read, write, and erase operations on the memory channels; and high priority and low priority queues coupled to the channel schedulers. The channel schedulers prioritize operations waiting in the high priority queues over operations waiting in the low priority queues. The channel schedulers further prioritize read operations waiting in either the high priority queue or the low priority queue over write and erase operations waiting in each respective queue.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: February 3, 2015
    Assignee: Virident Systems, Inc.
    Inventors: Vijay Karamcheti, Shibabrata Mondal, Ajith Kumar
  • Patent number: 8943245
    Abstract: A computing system is disclosed that includes a memory controller in a processor socket normally reserved for a processor. A plurality of non-volatile memory modules may be plugged into memory sockets normally reserved for DRAM memory modules. The non-volatile memory modules may be accessed using a data communication protocol to access the non-volatile memory modules. The memory controller controls read and write accesses to the non-volatile memory modules. The memory sockets are coupled to the processor socket by printed circuit board traces. The data communication protocol to access the non-volatile memory modules is communicated over the printed circuit board traces and through the sockets normally used to access DRAM type memory modules.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: January 27, 2015
    Assignee: Virident Systems, Inc.
    Inventors: Vijay Karamcheti, Kumar Ganapathy, Kenneth Alan Okin, Rajesh Parekh
  • Patent number: 8881389
    Abstract: In one implementation, flash memory chips are provided with an operating power supply voltage to substantially match a power supply voltage expected at an edge connector of a dual inline memory module. The one or more of the flash memory chips and a memory support application integrated circuit (ASIC) may be mounted together into a multi-chip package for integrated circuits. The one or more flash memory chips and the memory support ASIC may be electrically coupled together by routing one or more conductors between each in the multi-chip package. The multi-chip package may be mounted onto a printed circuit board (PCB) of a flash memory DIMM to reduce the number of packages mounted thereto and reduce the height of the flash memory DIMM. The number of printed circuit board layers may also be reduced, such as by integrating address functions into the memory support ASIC.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: November 11, 2014
    Assignee: Virident Systems, Inc.
    Inventors: Ruban Kanapathippillai, Kenneth Alan Okin
  • Patent number: 8874843
    Abstract: A translating memory module is disclosed including a printed circuit board, at least one memory integrated circuit coupled to the printed board, and at least one support chip coupled to the printed circuit board and coupled between the edge connector and the at least one memory integrated circuit. The at least one support chip includes a bi-directional translator to translate between a first memory communication protocol for the at least one memory integrated circuit and a second memory communication protocol for a memory channel differing from the first memory communication protocol. The second memory communication protocol to communicate data, address, and control signals over the memory channel bus to read and write data into the memory of the translating memory module.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: October 28, 2014
    Assignee: Virident Systems, Inc.
    Inventors: Kenneth Alan Okin, George Moussa, Kumar Ganapathy, Vijay Karamcheti, Rajesh Parekh
  • Patent number: 8856464
    Abstract: In one embodiment of the invention, a system is disclosed including a master memory controller and a plurality of memory modules coupled to the master memory controller. Each memory module includes a plurality of read-writeable non-volatile memory devices in a plurality of memory slices to form a two-dimensional array of memory. Each memory slice in each memory module includes a slave memory controller coupled to the master memory controller. When the master memory controller issues a memory module request, it is partitioned into a slice request for each memory slice.
    Type: Grant
    Filed: February 11, 2009
    Date of Patent: October 7, 2014
    Assignee: Virident Systems, Inc.
    Inventors: Vijay Karamcheti, Kumar Ganapathy
  • Patent number: 8850091
    Abstract: In one embodiment of the invention, a memory apparatus for improved write performance is disclosed. The memory apparatus includes a base printed circuit board (PCB) having an edge connector for plugging into a host server system; a card level power source to provide card level power during a power failure; a memory controller coupled to the card level power source and having one or more memory channels; and one or more non-volatile memory devices (NVMDs) coupled to the card level power source and organized to respectively couple to the memory channels controlled by the memory controller. Each memory controller provides queuing and scheduling of memory operations on a channel for each NVMD in the memory channels. Responsive to power failure, the memory controller receives card level power and changes the scheduling of memory operations to the NVMDs in each memory channel.
    Type: Grant
    Filed: January 20, 2013
    Date of Patent: September 30, 2014
    Assignee: Virident Systems, Inc.
    Inventors: Vijay Karamcheti, Ashwin Narasimha
  • Publication number: 20140258653
    Abstract: Data stored within symmetric and asymmetric memory components of main memory is integrated by identifying a first data as having access characteristics suitable for storing in an asymmetric memory component. The first data is included among a collection of data to be written to the asymmetric memory component. An amount of data is identified within the collection of data to be written to the asymmetric memory component. The amount of data is compared within the collection of data to a volume threshold to determine whether a block write to the asymmetric memory component is justified by the amount of data. If justified, the collection of data is loaded to the asymmetric memory component.
    Type: Application
    Filed: October 7, 2013
    Publication date: September 11, 2014
    Applicant: Virident Systems Inc.
    Inventors: Vijay Karamcheti, Kenneth A. Okin, Kumar Ganapathy, Ashish Singhai, Rajesh Parekh
  • Publication number: 20140258603
    Abstract: Main memory is managed by receiving a command from an application to read data associated with a virtual address that is mapped to the main memory. A memory controller determines that the virtual address is mapped to one of the symmetric memory components of the main memory, and accesses memory use characteristics indicating how the data associated with the virtual address has been accessed, The memory controller determines that the data associated with the virtual address has access characteristics suited to an asymmetric memory component of the main memory and loads the data associated with the virtual address to the asymmetric memory component of the main memory. After the loading and using the memory management unit, a command is received from the application to read the data associated with the virtual address, and the data associated with the virtual address is retrieved from the asymmetric memory component.
    Type: Application
    Filed: October 7, 2013
    Publication date: September 11, 2014
    Applicant: Virident Systems Inc.
    Inventors: Vijay Karamcheti, Kenneth A. Okin, Kumar Ganapathy, Ashish Singhai, Rajesh Parekh
  • Patent number: 8806116
    Abstract: In one embodiment of the invention, a memory module is disclosed including a printed circuit board with an edge connector; an address controller coupled to the printed circuit board; and a plurality of memory slices. Each of the plurality of memory slices of the memory module includes one or more memory integrated circuits coupled to the printed circuit board, and a slave memory controller coupled to the printed circuit board and the one or more memory integrated circuits. The slave memory controller receives memory access requests for the memory module from the address controller. The slave memory controller selectively activates one or more of the one or more memory integrated circuits in the respective memory slice in response to the address received from the address controller to read data from or write data into selected memory locations in the memory integrated circuits.
    Type: Grant
    Filed: February 11, 2009
    Date of Patent: August 12, 2014
    Assignee: Virident Systems, Inc.
    Inventors: Vijay Karamcheti, Kumar Ganapathy
  • Patent number: 8782373
    Abstract: A command from an application is received to access a data structure associated with one or more virtual addresses mapped to main memory. A first subset of the virtual addresses for the data structure having constituent addresses that are mapped to the symmetric memory components and a second subset of the virtual addresses for the data structure having constituent addresses that are mapped to the asymmetric memory components are identified. Data associated with the virtual address from the first physical addresses and data associated with the virtual addresses from the second physical addresses are accessed. The data associated with the symmetric and asymmetric memory components is accessed by the application without providing the application with an indication of whether the data is accessed within the symmetric memory component or the asymmetric memory component.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: July 15, 2014
    Assignee: Virident Systems Inc.
    Inventors: Vijay Karamcheti, Kenneth A. Okin, Kumar Ganapathy, Ashish Singhai, Rajesh Parekh
  • Patent number: 8745314
    Abstract: In one embodiment of the invention, a memory apparatus is disclosed. The memory apparatus includes a memory array, a block read/write controller, and a random access read memory controller. The memory array is block read/write accessible and random read accessible. The block read/write controller is coupled between the memory array and an external interconnect. The block read/write controller performs block read/write operations upon the memory array to access blocks of consecutive memory locations therein. The random access read memory controller is coupled between the memory array and the external interconnect in parallel with the block read/write access controller. The random access read memory controller performs random read memory operations upon the memory array to access random memory locations therein.
    Type: Grant
    Filed: June 24, 2009
    Date of Patent: June 3, 2014
    Assignee: Virident Systems, Inc.
    Inventors: Vijay Karamcheti, Kenneth A. Okin, Kumar Ganapathy
  • Patent number: 8706932
    Abstract: In one embodiment of the invention, a replaceable memory apparatus is disclosed. The replaceable memory apparatus includes a first rectangular multilayer printed circuit board having a first side and a second side opposite the first side; a first male pluggable electrical connector mounted to the first side near a first edge; a first female pluggable electrical connector mounted to the second side; and first non-volatile memory mounted to the first side and the second side. The first female pluggable electrical connector is coupled to the first male pluggable electrical connector to feed through first signals. The first non-volatile memory is coupled to the first female pluggable electrical connector and the first male pluggable electrical connector to receive the first signals.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: April 22, 2014
    Assignee: Virident Systems, Inc.
    Inventors: Ruban Kanapathippillai, Ashwin Narasimha, Kenneth A. Okin, Vijay Karamcheti
  • Patent number: 8689042
    Abstract: In one embodiment of the invention, a replaceable memory apparatus is disclosed. The replaceable memory apparatus includes a first rectangular multilayer printed circuit board having a first side and a second side opposite the first side; a first male pluggable electrical connector mounted to the first side near a first edge; a first female pluggable electrical connector mounted to the second side; and first non-volatile memory mounted to the first side and the second side. The first female pluggable electrical connector is coupled to the first male pluggable electrical connector to feed through first signals. The first non-volatile memory is coupled to the first female pluggable electrical connector and the first male pluggable electrical connector to receive the first signals.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: April 1, 2014
    Assignee: Virident Systems, Inc.
    Inventors: Ruban Kanapathippillai, Ashwin Narasimha, Kenneth A. Okin, Vijay Karamcheti
  • Patent number: 8677037
    Abstract: In one embodiment of the invention, a memory apparatus for improved write performance is disclosed. The memory apparatus includes a base printed circuit board (PCB) having an edge connector for plugging into a host server system; a card level power source to provide card level power during a power failure; a memory controller coupled to the card level power source and having one or more memory channels; and one or more non-volatile memory devices (NVMDs) coupled to the card level power source and organized to respectively couple to the memory channels controlled by the memory controller. Each memory controller provides queuing and scheduling of memory operations on a channel for each NVMD in the memory channels. Responsive to power failure, the memory controller receives card level power and changes the scheduling of memory operations to the NVMDs in each memory channel.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: March 18, 2014
    Assignee: Virident Systems, Inc.
    Inventors: Vijay Karamcheti, Ashwin Narasimha