Abstract: A method of providing one or more computing devices with access to a plurality of resources. The plurality of resources are provided by at least one physical device. The method comprises, at a first control element receiving a data packet transmitted by one of said one or more computing devices, and determining whether said data packet comprises a command including a first logical identifier identifying one of said resources. If it is determined that said data packet comprises a command including a first logical identifier a second logical identifier is obtained, the second logical identifier being associated with said first logical identifier and identifying said one of said resources. A request including said second logical identifier is transmitted to a second control element, the second control element being arranged to identify a physical device associated with said second logical identifier and to forward said request to the identified physical device.

Abstract: A method and apparatus for processing data packets. Each data packet comprises data intended to indicate a source of the data packet. The method comprises creating a data packet at a control element. The data of the second data packet intended to indicate a source of the second data packet comprises data indicating the first source, and further comprises data indicating that the second data packet was created by the control element, the second data packet is transmitted to a destination.

Abstract: A data switch for an integrated circuit comprising at least one link for receiving input data packets from an independently modulated spread spectrum clock (SSC) enabled source having predetermined spread spectrum link clock frequency characteristics, and at least one output for transmitting the data packets after passage through the switch, the switch further comprising at least one receive buffer having a link side and a core side for receiving the SSC modulated input data packets from the link, at least one transmit buffer and a core clock, wherein the core clock operates at a given frequency between predetermined error limits determined by oscillation accuracy alone and is not SSC-enabled, the core clock frequency being set at a level at least as high as the highest link clock frequency such that the receive buffer cannot be filled faster from its link side than it can be emptied from its core side.

Abstract: A data switch for an integrated circuit comprising at least one link for receiving input data packets from an independently modulated spread spectrum clock (SSC) enabled source having predetermined spread spectrum link clock frequency characteristics, and at least one output for transmitting the data packets after passage through the switch, the switch further comprising at least one receive buffer having a link side and a core side for receiving the SSC modulated input data packets from the link, at least one transmit buffer and a core clock, wherein the core clock operates at a given frequency between predetermined error limits determined by oscillation accuracy alone and is not SSC-enabled, the core clock frequency being set at a level at least as high as the highest link clock frequency such that the receive buffer cannot be filled faster from its link side than it can be emptied from its core side.

Abstract: A method of switching data packets between an input and a plurality of outputs of a switching device. The switching device comprises a memory arranged to store a plurality of data structures, each data structure being associated with one of said outputs. The method comprises receiving a first data packet at said input, and storing said first data packet in a data structure associated with an output from which said data packet is to be transmitted. If said first data packet is intended to be transmitted from a plurality of said outputs, indication data is stored in each data structure associated with an output from which said first data packet is to be transmitted, but said first data packet is stored in only one of said data structures. The first data packet is transmitted from said data structure to the or each output from which the first data packet is to be transmitted.

Abstract: A method for providing identifiers for virtual devices in a network. The method comprises receiving a discovery data packet directed to a physical network node associated with a physical endpoint device. A response to the discovery data packet directed to a physical network node is provided, the response comprising an identifier of a virtual device. At least one further discovery data packet directed at least to said virtual device is received. A response to a first one of the further discovery data packets is provided, the response comprising an identifier of a virtual endpoint device. At least some functionality of the virtual endpoint device is provided by the physical endpoint device.

Abstract: The present invention relates to a clock recovery circuit for generation of a recovered clock signal from a received data stream using a weighted combination of phase component signals. The clock recovery circuit comprises: a detector to detect the phase of a received data stream; a selector comprising a differential generator arranged to generate at least two related signals in dependence on the detected phase; and a clock signal generator to receive the at least two related signals and select related proportions of two or more of a plurality of phase component signals for combination, thereby to generate a recovered clock signal.

Abstract: There is disclosed a data switch in combination with a proxy controller, the data switch being configured for routing data traffic and control traffic between at least one input/output (I/O) device and at least one server including a memory having an address space including set of data buffers and a list of command/status descriptors. The data switch is configured to: i) distinguish between different types of traffic by examining packet headers; ii) route data traffic directly between the at least one I/O device and the at least one server; and iii) route control traffic by way of the proxy controller. In this way, I/O devices can be virtualised, since only the control traffic (which generally comprises less than 10% of the bandwidth) needs be processed by the proxy controller.

Abstract: A data switch for an integrated circuit comprising at least one link for receiving input data packets from an independently modulated spread spectrum clock (SSC) enabled source having predetermined spread spectrum link clock frequency characteristics, and at least one output for transmitting the data packets after passage through the switch, the switch further comprising at least one receive buffer having a link side and a core side for receiving the SSC modulated input data packets from the link, at least one transmit buffer and a core clock, wherein the core clock operates at a given frequency between predetermined error limits determined by oscillation accuracy alone and is not SSC-enabled, the core clock frequency being set at a level at least as high as the highest link clock frequency such that the receive buffer cannot be filled faster from its link side than it can be emptied from its core side.