Patents Assigned to Virtium Technology, Inc.
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Patent number: 9305655Abstract: Reduced spatial redundancy of lower bits data provides data protection for a flash memory having MLC NAND devices operated in page mode. An interrupted write operation of most significant bit pages can corrupt previously written data in lower bit pages. The lower bits redundant memory assists in restoring the data, using less than a full back up storage.Type: GrantFiled: September 27, 2013Date of Patent: April 5, 2016Assignee: Virtium Technology, Inc.Inventor: Lan Dinh Phan
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Publication number: 20150317083Abstract: Flash memory devices can be implemented with deduplication mechanism through a synergetic deduplication mapping that combines the logical-to-physical address mapping of the flash memory devices with the deduplication mapping. A deduplication algorithm can be implemented in the application layer, which can freely communicate with the flash memory devices and perform computationally expensive operations.Type: ApplicationFiled: May 5, 2014Publication date: November 5, 2015Applicants: Virtium Technology, Inc., Lan Dinh PhanInventor: Lan Dinh Phan
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Patent number: 9099173Abstract: An embodiment is a technique to classify a flash device. Test data to a flash device are accessed in unscramble and scramble modes under a test mode. Error correcting code (ECC) results are recorded on the test data for the unscramble and scramble modes. A device quality figure is calculated based on the ECC results for the unscramble and scramble modes. The flash device is classified using the device quality figure.Type: GrantFiled: December 14, 2012Date of Patent: August 4, 2015Assignee: VIRTIUM TECHNOLOGY, INC.Inventors: Jian Chen, Phan F. Hoang
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Patent number: 9064716Abstract: An embodiment is a method and apparatus to stack devices. A first finished package level (FPL) device having a first grounded tested die (GTD) is reduced to nearly size of the first GTD. The first FPL has a first plurality of solder balls. The reduced first FPL device is attached to a first substrate to form a first device assembly.Type: GrantFiled: September 30, 2009Date of Patent: June 23, 2015Assignee: VIRTIUM TECHNOLOGY, INC.Inventors: Phan Hoang, Chinh Minh Nguyen
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Publication number: 20150092487Abstract: Reduced spatial redundancy of lower bits data can provide data protection for a flash memory having MLC NAND devices operated in page mode. An interrupted write operation of most significant bit pages can corrupt previously written data in lower bit pages. The lower bits redundant memory can assist in restoring the data, using less than a full back up storage.Type: ApplicationFiled: September 27, 2013Publication date: April 2, 2015Applicant: Virtium Technology, Inc.Inventor: Lan Dinh Phan
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Patent number: 8990484Abstract: N page counters are associated with N blocks in the flash subsystem. Each of the N page counters indicates a count of invalid pages in each corresponding block in the N blocks. A max heap structure is formed over the N page counters. At least one of the N page counters is updated each time the count changes. The max heap structure is updated each time the at least one of the N page counters is updated. A maximum value is retrieved from a highest level of the max heap structure. The max heap structure is traversed down to lowest level using the maximum value at each level until reaching the lowest level. The lowest level corresponds to N page counters. One of the N blocks having associated page counter corresponds to the maximum value is identified as a candidate for block erasure.Type: GrantFiled: December 14, 2012Date of Patent: March 24, 2015Assignee: Virtium Technology, IncInventor: Ho-Fan Kang
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Patent number: 8918583Abstract: An embodiment is a technique to adapt behavior of a solid-state drive (SSD) to extend lifespan of the SSD. Real environmental information is received from an environmental processor. The real environmental information corresponds to an environment of the SSD. A behavior model is selected based on a real environmental model and an internal data usage model. If a new behavior model is selected, the environmental processor is informed about the new behavior model. The environmental processor sends control commands to a power management module to apply new power policy to the SSD. Information on the new behavior model is made available for query. If current behavior model is selected, the current behavior model is maintained.Type: GrantFiled: December 20, 2012Date of Patent: December 23, 2014Assignee: Virtium Technology, Inc.Inventors: Pho Hoang, Jian Chen
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Patent number: 8784125Abstract: A side clip has a clip base attached to a socket connector and a first clip member and a second clip member extending from the clip base. The first clip member has a terminal for attaching to a printed circuit board. The second clip member is spaced in parallel from the first member and connected to the first clip member by a distal segment to form an opening. A side retainer has a retainer base having first and second ends and first, second, third, and fourth retainer members extending vertically from the retainer base. The first retainer member fits a hole on a board held by the side clip. The second retainer member is located at the first end and has an inward hook. The fourth retainer member is located on the second end and has an outward hook.Type: GrantFiled: June 27, 2012Date of Patent: July 22, 2014Assignee: Virtium Technology, Inc.Inventor: Phan F Hoang
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Publication number: 20140181595Abstract: An embodiment is a technique to estimate lifespan of a solid-state drive (SSD). Real environmental information from an environmental processor is received. The real environmental information corresponds to an environment of a solid-state drive (SSD). The lifespan of the SSD is estimated using the real environmental information and an internal data usage model. The estimated lifespan is made available for retrieval.Type: ApplicationFiled: December 20, 2012Publication date: June 26, 2014Applicant: Virtium Technology, Inc.Inventors: Pho Hoang, Jian Chen
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Publication number: 20140181434Abstract: An embodiment is a technique to perform static wear leveling in a flash device. A first static block is popped from front of a first-in-first-out (FIFO) static pool when a static wear leveling condition is met. Data are copied from the first static block into an erased block to form a new block. The new block is pushed to end of the FIFO static pool. The static pool is part of a current static set and a next static set. Another embodiment is a technique to maintain a FIFO static pool. All valid data are consolidated when a data collection condition is met. An erased block is selected from a free set. All consolidated data are copied into the erased block to form a new block. The new block is pushed into the FIFO static pool.Type: ApplicationFiled: December 20, 2012Publication date: June 26, 2014Applicant: Virtium Technology, Inc.Inventors: Trevor Chau, Lan Dinh Phan
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Publication number: 20140181585Abstract: An embodiment is a technique to generate failure mode information for solid-state drive (SSD) in real environment. An environmental acquisition module acquires environmental information from an environmental sensor. A learning and update module generates an environmental profile based on the acquired environmental information. A failure acquisition module associates failure information from an SSD controller that controls an SSD with the environmental profile. An operation analyzer analyzes the associated failure information using pre-determined information provided by a database to generate failure mode information. A decision module decides if the failure mode information is valid.Type: ApplicationFiled: December 20, 2012Publication date: June 26, 2014Applicant: Virtium Technology, Inc.Inventors: Pho Hoang, Jian Chen
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Publication number: 20140181363Abstract: An embodiment is a technique to adapt behavior of a solid-state drive (SSD) to extend lifespan of the SSD. Real environmental information is received from an environmental processor. The real environmental information corresponds to an environment of the SSD. A behavior model is selected based on a real environmental model and an internal data usage model. If a new behavior model is selected, the environmental processor is informed about the new behavior model. The environmental processor sends control commands to a power management module to apply new power policy to the SSD. Information on the new behavior model is made available for query. If current behavior model is selected, the current behavior model is maintained.Type: ApplicationFiled: December 20, 2012Publication date: June 26, 2014Applicant: Virtium Technology, Inc.Inventors: Pho Hoang, Jian Chen
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Publication number: 20140172325Abstract: An embodiment is a method and apparatus for a technique to report remaining life information of a non-volatile memory array. Information on expected life of a non-volatile memory array is received from a solid-state drive (SSD) processor. The information is converted into remaining life information according to a pre-defined format. The remaining life information is transmitted to an indicator or a communication device.Type: ApplicationFiled: December 14, 2012Publication date: June 19, 2014Applicant: Virtium Technology, Inc.Inventor: Ashraf M. Naji
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Publication number: 20140173176Abstract: N page counters are associated with N blocks in the flash subsystem. Each of the N page counters indicates a count of invalid pages in each corresponding block in the N blocks. A max heap structure is formed over the N page counters. At least one of the N page counters is updated each time the count changes. The max heap structure is updated each time the at least one of the N page counters is updated. A maximum value is retrieved from a highest level of the max heap structure. The max heap structure is traversed down to lowest level using the maximum value at each level until reaching the lowest level. The lowest level corresponds to N page counters. One of the N blocks having associated page counter corresponds to the maximum value is identified as a candidate for block erasure.Type: ApplicationFiled: December 14, 2012Publication date: June 19, 2014Applicant: Virtium Technology, Inc.Inventor: Ho-Fan Kang
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Publication number: 20140173369Abstract: An embodiment is a technique to classify a flash device. Test data to a flash device are accessed in unscramble and scramble modes under a test mode. Error correcting code (ECC) results are recorded on the test data for the unscramble and scramble modes. A device quality figure is calculated based on the ECC results for the unscramble and scramble modes. The flash device is classified using the device quality figure.Type: ApplicationFiled: December 14, 2012Publication date: June 19, 2014Applicant: Virtium Technology, Inc.Inventors: Jian Chen, Phan F. Hoang
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Publication number: 20140173175Abstract: An embodiment is a method and apparatus to provide an optimization of commands in a flash device. Commands sent by at least a top-level processor to a flash device are buffered in a buffer. The buffered commands are analyzed for an optimizing condition. The commands are aggregated if the optimizing condition is met. The aggregated commands are sent to the flash device.Type: ApplicationFiled: December 14, 2012Publication date: June 19, 2014Applicant: Virtium Technology, Inc.Inventors: Ho-Fan Kang, Lan Dinh Phan
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Patent number: 8124450Abstract: An embodiment of the present invention is a technique to stack multiple devices using an interconnecting element. A board has a periphery and top and bottom surfaces. The top surface has top contact pads to attach to a first device. The bottom surface is milled down to form a cavity confined by vertical walls around the periphery. The cavity fits a second device. Bottom contact pads are formed on bottom side of the vertical walls. The bottom contact pads are raised with respect to the bottom side of the vertical walls. Traces internal to the board connect the bottom contact pads to the top contact pads.Type: GrantFiled: July 27, 2010Date of Patent: February 28, 2012Assignee: Virtium Technology, Inc.Inventors: Phan Hoang, Chinh Nguyen, Anthony Tran, Tung Dang
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Patent number: 8090988Abstract: An embodiment is a method and apparatus to save data during power failure. A power supply generator generates operating voltages to a circuit from a generator supply source. A power monitor monitors a normal supply voltage and a backup supply voltage to provide a normal supply voltage to the generator supply source in a normal mode and to provide a backup supply voltage to the generator supply source in a power failure mode. A data transfer circuit transfers data from a volatile memory in the circuit to a non-volatile memory during the power failure mode.Type: GrantFiled: November 24, 2009Date of Patent: January 3, 2012Assignee: Virtium Technology, Inc.Inventor: Phan Hoang
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Patent number: 8028404Abstract: An embodiment is a method and apparatus to provide a multi-function module. A circuit board has a form factor and a connector edge corresponding to a first interface standard. The connector edge includes first and second groups of pin-outs that are mapped to pin-out assignments compatible with the first interface standard and a second interface standard, respectively. A first interface is provided on the circuit board for a first set of devices connected to the first group of pin-outs to operate according to the first interface standard. A second interface is provided on the circuit board for a second set of devices connected to the second group of pin-outs to operate according to the second interface standard.Type: GrantFiled: June 17, 2010Date of Patent: October 4, 2011Assignee: Virtium Technology, Inc.Inventor: Phan Hoang
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Publication number: 20110126046Abstract: An embodiment is a method and apparatus to save data during power failure. A power supply generator generates operating voltages to a circuit from a generator supply source. A power monitor monitors a normal supply voltage and a backup supply voltage to provide a normal supply voltage to the generator supply source in a normal mode and to provide a backup supply voltage to the generator supply source in a power failure mode. A data transfer circuit transfers data from a volatile memory in the circuit to a non-volatile memory during the power failure mode.Type: ApplicationFiled: November 24, 2009Publication date: May 26, 2011Applicant: VIRTIUM TECHNOLOGY, INC.Inventor: Phan Hoang