Abstract: A resolution enhancement circuit comprises a voltage divider used to add multiples of two position representing quadrature signals into a plurality of adder output signals having zero crossings during the cycle of the quadrature signals, a digitizer creating a plurality digital signals based on the individual adder output signals and an output logic circuit combining the digital signals into a new pair of digital quadrature signals of increased resolution. The circuit provides information for more precise control of die casting machines and the like.