Abstract: Ultra-low drain-source resistance power MOSFET. In accordance with an embodiment of the preset invention, a semiconductor device comprises a plurality of trench power MOSFETs. The plurality of trench power MOSFETs is formed in a second epitaxial layer. The second epitaxial layer is formed adjacent and contiguous to a first epitaxial layer. The first epitaxial layer is formed adjacent and contiguous to a substrate highly doped with red Phosphorous. The novel red Phosphorous doped substrate enables a desirable low drain-source resistance.
Type:
Grant
Filed:
March 21, 2006
Date of Patent:
April 2, 2013
Assignee:
Vishay-Silconix
Inventors:
The-Tu Chau, Sharon Shi, Qufei Chen, Martin Hernandez, Deva Pattanayak, Kyle Terrill, Kuo-In Chen