Abstract: A static random access memory has a multiplicity of separate memory blocks, only one of which is activated during each memory access cycle. Each memory block has its own separate bit line equalization circuity which equalizes the voltages of each complementary bit line pair in the memory block. A write equalization decoder automatically, at the end of each write cycle, generates a decoded write recovery equalization pulse, which activates the bit line equalization circuitry only in the memory block to which data has been written. As a result, the process of equalizing the bit lines is removed from the critical timing path for accessing the memory after a write cycle, eliminating one of the primary problems associated with the use of address transition detection in static memory devices. In addition, the write recovery equalization pulse can be generated at high speed because the decoded write recovery equalization pulse drives only one of the multiplicity of separate memory blocks.

Abstract: A static random access memory having a plurality of pairs of common data out lines. A plurality of bit line pairs are coupled to each pair of common data out lines. The common data out lines are automatically equalized at the end of each memory access cycle, and the accessed bit lines are automatically equalized at the end of each write cycle. Thus, the process of equalizing the common data out lines is removed from the critical timing path for accessing the memory, which eliminates one of the primary problems in the use of address transition detection in static memory devices.