Abstract: A power switch comprising: a cascode having a normally ON transistor connected in series with a normally OFF transistor at a cascode node: a first diode connected between a gate of the normally ON transistor and a first ground common to the cascode and the diode; and a controller comprising: a controller power supply having a power supply output connected to the cascode node at which output the controller power supply provides a voltage relative to a second ground that is floating relative to the first ground; and a first controller output connected to the gate of the normally ON transistor at which the controller generates a first voltage relative to the second ground.

Abstract: A field effect transistor (FET) includes a plurality of substantially parallel conductive channels and at least one electrically conducting plug to travers and form an ohmic connection with at least two of the plurality of conductive channels.

Abstract: A voltage pulse generator comprising: circuitry controllable to generate a voltage pulse at an output of the circuitry; and an interruptor that monitors voltage at the output during a transition edge of the voltage pulse and interrupts a voltage change associated with the transition edge if the monitored voltage differs from a predetermined reference voltage by a predetermined amount.

Abstract: A device for switching a high-voltage source, comprising: a plurality of switching devices coupled in series starting from a first switching device and ending in a last switching device, said device enabling coupling of said high-voltage source with at least a selected one of said switching devices; a voltage limiter coupled with said switching devices; and a switching time synchronizer; wherein said first switching device is configured to directly receive a control signal for changing a switching state of said device, said first switching device is configured to facilitate a cascaded transition of switching states in successive said switching devices in said series, where said switching time synchronizer is configured to synchronize a time at which transitions to said switching states of successive said switching devices take effect, and said voltage limiter is configured to limit overvoltage conditions to said switching devices during said transitions.

Abstract: A GaN field effect transistor (FET) including a plurality of transistor cells. A gate metal layer of a transistor cell includes a gate-drain overhang (width 0.2 um to 2.5 um) and a gate-source overhang (width 0.3 um to 1 um), and a widening at each narrow edge of the transistor cell, wherein the width of the widening of gate metal layer (150) is of 2-5 um. A metal (1) layer of the transistor sell extends beyond metal (0) layer. A last metal layer includes a drain plate and a source plate, each having a trapezoid form. More than two vias are located at a widening for connecting the gate metal layer to the gate bus. More than six vias distributed along the longitudinal dimension of the transistor cell connect metal (1) layer to metal (0) layer. A plurality of type 2 vias connect metal (1) layer to the last metal layer.

Abstract: A switching power device (100) is provided which comprises: a normally-ON transistor (12), a normally-OFF metal-oxide-semiconductor field-effect transistor (MOSFET) (14), the normally-OFF MOSFET (14) being connected in series to a source terminal (12S) of the normally-ON transistor (12), and a driver (16) connected to and arranged to drive a gate terminal (12G) of the normally-ON transistor (12). A switching transistor (28) can then be positioned between the source terminal (12S) of the normally-ON transistor (12) and a common connection (30) of the driver (16) to protect the switching power device (100) from deleterious over-voltage and over-current spikes.

Abstract: A GaN field effect transistor (FET) including a plurality of transistor cells. A gate metal layer of a transistor cell includes a gate-drain overhang (width 0.2 um to 2.5 um) and a gate-source overhang (width 0.3 um to 1 um), and a widening at each narrow edge of the transistor cell, wherein the width of the widening of gate metal layer (150) is of 2-5 um. A metal (1) layer of the transistor sell extends beyond metal (0) layer. A last metal layer includes a drain plate and a source plate, each having a trapezoid form. More than two vias are located at a widening for connecting the gate metal layer to the gate bus. More than six vias distributed along the longitudinal dimension of the transistor cell connect metal (1) layer to metal (0) layer. A plurality of type 2 vias connect metal (1) layer to the last metal layer.

Abstract: An apparatus includes a circuitry to perform a high current and/or a high voltage switching. The circuitry includes a first Gallium Nitride (GaN) on a silicon (Si) substrate lateral field effect transistor. A source terminal of the first GaN lateral field effect transistor on the Si substrate includes an electrical connection to backside of P-type Si substrate through a high voltage isolated resistor that is coupled to a source terminal or a second resistor that is operably coupled to a drain terminal and a substrate terminal. The high voltage isolated resistor and the second resistor cause to a leakage current from the drain terminal to the source terminal via a buffer layer. The leakage current equalizes the voltage drop on the first GaN lateral field effect transistor on the Si substrate to a voltage drop on a serially connected second GaN lateral field effect transistor on the Si substrate.

Abstract: A switching power device (100) is provided which comprises: a normally-ON transistor (12), a normally-OFF metal-oxide-semiconductor field-effect transistor (MOSFET) (14), the normally-OFF MOSFET (14) being connected in series to a source terminal (12S) of the normally-ON transistor (12), and a driver (16) connected to and arranged to drive a gate terminal (12G) of the normally-ON transistor (12). A switching transistor (28) can then be positioned between the source terminal (12S) of the normally-ON transistor (12) and a common connection (30) of the driver (16) to protect the switching power device (100) from deleterious over-voltage and over-current spikes.

Abstract: An apparatus includes a circuitry to perform a high current and/or a high voltage switching. The circuitry includes a first Gallium Nitride (GaN) on a silicon (Si) substrate lateral field effect transistor. A source terminal of the first GaN lateral field effect transistor on the Si substrate includes an electrical connection to backside of P-type Si substrate through a high voltage isolated resistor that is coupled to a source terminal or a second resistor that is operably coupled to a drain terminal and a substrate terminal. The high voltage isolated resistor and the second resistor cause to a leakage current from the drain terminal to the source terminal via a buffer layer. The leakage current equalizes the voltage drop on the first GaN lateral field effect transistor on the Si substrate to a voltage drop on a serially connected second GaN lateral field effect transistor on the Si substrate.

Abstract: A field effect transistor (FET) comprises a plurality of substantially parallel conductive channels (252, 254) and at least one electrically conducting plug (209) that traverses and forms an ohmic connection with at least two of the plurality of conductive channels.

Abstract: A normally OFF field effect transistor (FET) comprising: a plurality of contiguous nitride semiconductor layers having different composition and heterojunction interfaces between contiguous layers, a Fermi level, and conduction and valence energy bands; a source and a drain overlying a top nitride layer of the plurality of nitride layers and having source and drain access regions respectively comprising regions of at least two of the heterojunctions near the source and drain; a first gate between the source and drain; wherein when there is no potential difference between the gates and a common ground voltage, a two dimensional electron gas (2DEG) is present in the access region at a plurality of heterojunctions in each of the source and drain access regions, and substantially no 2DEG is present adjacent any regions of the heterojunctions under the first gate.

Abstract: An embodiment of the invention relates to a semiconductor device comprising: first and second electrodes comprising first and second busbars respectively that decrease in cross section in opposite directions; and a plurality of interleaving first and second conducting fingers that extend from the first and second busbars respectively.

Abstract: An embodiment of the invention relates to a semiconductor device comprising: first and second electrodes comprising first and second busbars respectively that decrease in cross section in opposite directions; and a plurality of interleaving first and second conducting fingers that extend from the first and second busbars respectively.

Abstract: A normally OFF field effect transistor (FET) comprising: a plurality of contiguous nitride semiconductor layers having different composition and heterojunction interfaces between contiguous layers, a Fermi level, and conduction and valence energy bands; a source and a drain overlying a top nitride layer of the plurality of nitride layers and having source and drain access regions respectively comprising regions of at least two of the heterojunctions near the source and drain; a first gate between the source and drain; wherein when there is no potential difference between the gates and a common ground voltage, a two dimensional electron gas (2DEG) is present in the access region at a plurality of heterojunctions in each of the source and drain access regions, and substantially no 2DEG is present adjacent any regions of the heterojunctions under the first gate.

Abstract: A normally OFF field effect transistor (FET) having a plurality of contiguous nitride semiconductor layers having different composition and heterojunction interfaces, wherein when there is no potential difference between a first gate and a common ground voltage, a two dimensional electron gas (2DEG) is present at a plurality of heterojunctions in each of a source access region and a drain access region, and substantially no 2DEG is present adjacent any regions of the heterojunctions under the first gate.

Abstract: A normally OFF field effect transistor (FET) comprising: a plurality of contiguous nitride semiconductor layers having different composition and heterojunction interfaces between contiguous layers, a Fermi level, and conduction and valence energy bands; a source and a drain overlying a top nitride layer of the plurality of nitride layers and having source and drain access regions respectively comprising regions of at least two of the heterojunctions near the source and drain; a first gate between the source and drain; wherein when there is no potential difference between the gates and a common ground voltage, a two dimensional electron gas (2DEG) is present in the access region at a plurality of heterojunctions in each of the source and drain access regions, and substantially no 2DEG is present adjacent any regions of the heterojunctions under the first gate.