Abstract: A static random access memory has a multiplicity of separate memory blocks, only one of which is activated during each memory access cycle. Each memory block has its own separate bit line equalization circuity which equalizes the voltages of each complementary bit line pair in the memory block. A write equalization decoder automatically, at the end of each write cycle, generates a decoded write recovery equalization pulse, which activates the bit line equalization circuitry only in the memory block to which data has been written. As a result, the process of equalizing the bit lines is removed from the critical timing path for accessing the memory after a write cycle, eliminating one of the primary problems associated with the use of address transition detection in static memory devices. In addition, the write recovery equalization pulse can be generated at high speed because the decoded write recovery equalization pulse drives only one of the multiplicity of separate memory blocks.

Abstract: A static random access memory having a plurality of pairs of common data out lines. A plurality of bit line pairs are coupled to each pair of common data out lines. The common data out lines are automatically equalized at the end of each memory access cycle, and the accessed bit lines are automatically equalized at the end of each write cycle. Thus, the process of equalizing the common data out lines is removed from the critical timing path for accessing the memory, which eliminates one of the primary problems in the use of address transition detection in static memory devices.

Abstract: A sense amplifier for use in a CMOS static random access memory. The core of the sense amplifier comprises seven transistors: two sensing transistors with their sources coupled to a common pull down node, a pull down transistor for drawing current from the pull down node during sensing operations, and a four transistor latch coupled to the drains of the two sensing transistors. The four transistor latch comprises two cross coupled CMOS inverters. When the pull down transistor is activated, the four transistor latch automatically amplifies the voltage differential on the gates of the two sensing transistors, typically latching in less than two nanoseconds. Since the latch is made up of CMOS inverters, no d.c. current is drawn by the sense amplifier after the input data has been sensed and latched. As a result, relatively powerful transistors can be used in the sense amplifier.

Abstract: A semiconductor memory device having an improved system for randomly accessing a preselected set of memory locations. The invention includes a set of "secondary sense amplifiers" which act as a high speed buffer between the memory's normal sense amplifiers and the memory's data input and output buffers. The secondary sense amplifiers are connected to selected ones of the sense amplifiers in accordance with a first predefined subset of the memory's column address signals. A decoder circuit, which is directly responsive to a second predefined subset of the column address signals, selects one of the secondary sense amplifiers and connects it to the memory's data input and output buffers. Since the decoder is directly responsive to the second predefined subset of the column address signals and does not need to latch in new address values after the detection of an address signal transition, all the secondary sense amplifiers can be accessed much faster than the other data storage locations in the memory.

Abstract: A memory array of four-IGFET-transistor cells arranged in rows and columns. The array uses two patterned metal layers and two patterned poly-silicon layers. For each column there is a pair of metal differential bit lines, formed on a first patterned metal layer. For each row there is a pair of split equipotential poly-silicon word lines and a parallel metal word line with connections to the split poly word lines at defined intervals. The parallel metal word line is on a second patterned metal layer distinct from the metal layer used for the bit lines. A grounded poly-silicon plate overlies the capacitive memory nodes of said array. The grounded poly-silicon plate is on a second patterned poly-silicon layer distinct from the poly-silicon layer used for the split word lines. The poly-silicon plate is connected to the circuit ground at defined intervals. Also, the poly-silicon plate provides alpha particle protection to the array and helps decouple the bit lines from the capacitive nodes of the array.

Abstract: There is provided an improved MOS dynamic random access memory (DRAM) device having an array of dynamic RAM cells accessed by word and bit lines. Each memory cell comprises a single field-effect transistor coupled by its source to the gate of an MOS storage capacitor. The word lines are coupled to their respective memory cells at the gate of the field-effect transistor therein, while the bit lines are coupled to their respective memory cells at the drain of the field-effect transistor. The bit lines are organized into pairs of adjacent polysilicon lines that are coupled to all the memory cells on both sides of the bit lines in an alternating configuration. The word lines are coupled to alternating pairs of cells on opposite sides of the word lines.

Abstract: There is described a CMOS random access memory having memory access circuitry which substantially eliminates substrate noise caused by capacitive coupling of the bit lines to the substrate, and which allows the memory to have equal length access and cycle times. Access circuitry for each column of cells includes a pair of differential bit lines, at least one bit line equalization transistor, and a CMOS sense amp. The sense amp has two p-channel pull-up transistors, each having its source node connected to a common pull-up node, and two n-channel pull-down transistors, each having its source node connected to a common pull-down node.At the beginning of each memory access cycle the differential bit lines are equalized and the common pull-up and pull-down nodes are equalized. Then, substantially simultaneously, the common pull-up node is charged while the common pull-down node is discharged.