Abstract: Provided is a high ruggedness heterojunction bipolar transistor (HBT), including a collector layer. The collector layer includes a InGaP layer or a wide bandgap layer. The bandgap of the InGaP layer is greater than 1.86 eV.

Abstract: The present invention is a semiconductor device having a defect blocking region. The semiconductor device includes a substrate, a defect source region, a semiconductor layer and a defect blocking region. The defect source region is on the substrate, wherein the defect source region is a metamorphic buffer layer or a buffer layer, the semiconductor layer over the defect source region, wherein a lattice constant of the semiconductor layer is different from a lattice constant of the substrate. The defect blocking region is disposed on the substrate and below the semiconductor layer, wherein the defect blocking region includes a superlattice structure, wherein at least one of two adjacent layers of the superlattice structure has strain relative to the semiconductor layer, or a lattice constant of the superlattice structure is close to or equal to the lattice constant of the semiconductor layer.

Abstract: Provided is a semiconductor laser diode, including a GaAs/In P substrate and a multi-layer structure on the GaAs/InP substrate. The multi-layer structure includes a lower epitaxial region, an active region and an upper epitaxial region. The active region comprises a first active layer, an epitaxial region and a second active layer, the epitaxial region is disposed between the first active layer and the second active layer, the first active layer comprises one or more quantum well structures or one or more quantum dot structures, and the second active layer comprises one or more quantum well structures or one or more quantum dot structures.

Abstract: Provided is a semiconductor epitaxial wafer, including a substrate, a first epitaxial structure, a first ohmic contact layer and a second epitaxial stack structure. It is characterized in that the ohmic contact layer includes a compound with low nitrogen content, and the ohmic contact layer does not induce significant stress during the crystal growth process. Accordingly, the second epitaxial stack structure formed on the ohmic contact layer can have good epitaxial quality, thereby providing a high-quality semiconductor epitaxial wafer for fabricating a GaAs integrated circuit or a InP integrated circuit. At the same time, the ohmic contact properties of ohmic contact layers are not affected, and the reactants generated during each dry etching process are reduced.

Abstract: Provided is a vertical cavity surface emitting laser diode (VCSEL) with low compressive strain DBR layer, including a GaAs substrate, a lower DBR layer, a lower spacer layer, an active region, an upper spacer layer and an upper DBR layer. The lower or the upper DBR layer includes multiple low refractive index layers and multiple high refractive index layers. The lower DBR layer, the lower spacer layer, the upper spacer layer or the upper DBR layer contains AlxGa1-xAs1-yPy, where the lattice constant of AlxGa1-xAs1-yPy is greater than that of the GaAs substrate. This can moderately reduce excessive compressive strain due to lattice mismatch or avoid tensile strain during the epitaxial growth, thereby reducing the chance of deformation and bowing of the VCSEL epitaxial wafer or cracking during manufacturing. Additionally, the VCSEL epitaxial layer can be prevented from generating excessive compressive strain or tensile strain during the epitaxial growth.

Abstract: A measurement method for a vertical cavity surface emitting laser diode (VCSEL) and an epitaxial wafer test fixture are provided, especially the Fabry-Perot Etalon of the bottom-emitting VCSEL can be measured. When the Fabry-Perot Etalon of the bottom-emitting VCSEL is measured by a measurement apparatus, a light of the test light source of the measurement apparatus is incident from the substrate surface of the VCSEL epitaxial wafer such that the Fabry-Perot Etalon of the bottom-emitting VCSEL is acquired. Through the VCSEL epitaxial wafer test fixture, the bottom-emitting VCSEL can be directly measured by the existing measurement apparatus such that there is no need to change the optical design of the measurement apparatus, and it can prevent the VCSEL epitaxial wafer from being scratched or contaminated.

Abstract: A laser diode is provided, including at least a defect blocking layer deposited between the GaAs substrate and the active layer, so that the crystal defects of the GaAs substrate can be blocked or reduced from propagation to the active layer when the epitaxial layer is formed on the GaAs substrate. As such, the crystal quality of the active layer can be improved, thereby improving the reliability and optical property of the laser diode.

Abstract: Provided is a high ruggedness HBT, including a first emitter cap layer and a second emitter cap layer formed between an emitter layer and an ohmic contact layer, or only an emitter cap layer is formed between them. When the first and second emitter cap layers are provided, bandgaps of the first or second emitter cap layer are changed, and the ruggedness of the HBT is improved. When an emitter cap layer is provided, an electron affinity of at least a portion of the emitter cap layer is less than or approximately equal to an electron affinity of the emitter layer, and the ruggedness of the HBT is improved.

Abstract: The disclosure provides a high ruggedness HBT structure, including: a sub-collector layer on a substrate and formed of an N-type III-V semiconductor material; a collector layer on the sub-collector layer and formed of a III-V semiconductor material; a base layer on the collector layer and formed of a P-type III-V semiconductor material; an emitter layer on the base layer and formed of one of N-type semiconductor materials of InGaP, InGaAsP and InAlGaP; a first emitter cap layer on the emitter layer and formed of one of undoped or N-type semiconductor materials of AlxGa1-xAs, AlxGa1-xAs1-yNy, AlxGa1-xAs1-zPz, AlxGa1-xAs1-wSbw, and InrAlxGa1-x-rAs, x having a highest value between 0.05?x?0.4, and y, z, r, w?0.1; a second emitter cap layer on the first emitter cap layer and formed of an N-type III-V semiconductor material; and an ohmic contact layer on the second emitter cap layer and formed of an N-type III-V semiconductor material.

Abstract: Provided is a heterojunction bipolar transistor (HBT) structure with a bandgap graded hole barrier layer, including: a sub-collector layer including an N-type group III-V semiconductor on a substrate, a collector layer on the sub-collector layer and including a group III-V semiconductor, a hole barrier layer on the collector layer, a base layer on the hole barrier layer and including a P-type group III-V semiconductor, an emitter layer on the base layer and including an N-type group III-V semiconductor, an emitter cap layer on the emitter layer and including an N-type group III-V semiconductor, and an ohmic contact layer on the emitter cap layer and including an N-type group III-V semiconductor. Bandgaps of the hole barrier layer at least include a gradually increasing bandgap from the base layer towards the collector layer and a largest bandgap of the hole barrier layer is greater than bandgap of the base layer.

Abstract: The disclosure provides an HBT structure with bandgap graded hole barrier layer, comprising: a sub-collector layer, a collector layer, a hole barrier layer, a base layer, an emitter layer, an emitter cap layer, and an ohmic contact layer, all stacked sequentially on a substrate; with the hole barrier layer formed of at least one of AlGaAs, AlGaAsN, AlGaAsP, AlGaAsSb, and InAlGaAs, Aluminum composition being less than 22%, and In, N, P, and Sb compositions being respectively less than or equal to 10%; wherein bandgaps of the hole barrier layer at least comprise a gradually increasing bandgap from the base layer towards the collector layer and the largest bandgap of the hole barrier layer is greater than bandgaps of the base layer and the collector layer.

Abstract: A directed epitaxial heterojunction bipolar transistor (HBT) structure is directly or indirectly formed on a GaAs substrate that is formed by a (100) face towards a (111)B face with an angle of inclination between 0.6° and 25°, and includes a sub-collector layer, a collector, a base layer, an emitter layer, an emitter cap layer and an ohmic contact layer, which are sequentially formed on the substrate. A tunnel collector layer formed by InGaP or InGaAsP is provided between the collector layer and the base layer. Since an epitaxial process is performed on the substrate from a (100) face towards a (111)B face with an angle of inclination between 0.6° and 25°, indium and gallium contained in InGaP or InGaAsP are affected by the ordering effect such that InGaP or InGaAsP used in the emitter layer and/or the tunnel collector layer has a higher electron affinity or a smaller bandgap.

Abstract: A high electron mobility bipolar transistor including a substrate, a pseudomorphic high electron mobility transistor (pHEMT) sub structure, a sub collector/separating layer and a heterojunction bipolar transistor (HBT) sub structure sequentially stacked from bottom to top is disclosed. The sub collector/separating layer and the pHEMT sub structure are combined to form a pHEMT, and the sub collector/separating layer and the HBT sub structure are combined to form an HBT. The carbon concentration in the sub collector/separating layer is within 5×1017 cm?3 and 1×1020 cm?3, and/or the oxygen concentration within 5×1018 cm?3 and 1×1020 cm?3. The lattice during the process of epitaxy growth is stabilized and it is possible to prevent the dopants, the elements, the vacancies or the defects from diffusing into the neighboring layers, thereby improving the problem of mobility degradation and resistance increase, and sustaining the stability of the manufacturing process.

Abstract: A high electron mobility bipolar transistor including a substrate, a pseudomorphic high electron mobility transistor (pHEMT) sub structure, a sub collector/separating layer and a heterojunction bipolar transistor (HBT) sub structure sequentially stacked from bottom to top is disclosed. The sub collector/separating layer and the pHEMT sub structure are combined to form a pHEMT, and the sub collector/separating layer and the HBT sub structure are combined to form an HBT. The carbon concentration in the sub collector/separating layer is within 5×1017 cm?3 and 1×1020 cm?3, and/or the oxygen concentration within 5×1018 cm?3 and 1×1020 cm?3. The lattice during the process of epitaxy growth is stabilized and it is possible to prevent the dopants, the elements, the vacancies or the defects from diffusing into the neighboring layers, thereby improving the problem of mobility degradation and resistance increase, and sustaining the stability of the manufacturing process.

Abstract: The HBT-based transient suppression device contains a collector layer of a first conduction type, a base layer of a second conduction type, an emitter layer of the first conduction type, stacked in this order sequentially on a top side of a heavily doped substrate of the first conduction type. The doping concentration of the base layer is higher than that of the emitter and collector layers, and that the thickness of the collector layer is less than 300 nm, so that the BVCEO breakdown voltage is reduced below 5V Additionally, the thickness of the base layer is larger than the sum of the thickness of a section of the emitter-base depletion region extending into the base layer and the thickness of a section of the base-collector depletion region extending into the base layer, so that the base layer is not operated in a punch-through condition.

Abstract: The invention provides a BiFET semiconductor device vertically integrating a FET and a HBT on the same substrate. The BiFET semiconductor device comprises a HBT structure, a high-resistivity structure, and a FET structure, sequentially formed in this order from bottom to top on a semi-insulating substrate. The high-resistivity structure comprises at least two layers. A first layer is on top of the HBT structure to provide the required high resistivity, while the second layer having a high purity is on top of the first layer to prevent the doped impurity in the first layer to affect the upper FET structure.

Abstract: A method for fabricating a high brightness LED structure is disclosed herein, which comprises at least the following steps. First, a first layered structure is provided by sequentially forming a light generating structure, a non-alloy ohmic contact layer, and a first metallic layer from bottom to top on a side of a first substrate. Then, a second layered structure comprising at least a second substrate is provided. Then, the two-layered structures are wafer-bonded together, with the top side of the second layered structure interfacing with the top side of said first layered structure. The first metallic layer functions as a reflective mirror, which is made of a pure metal or a metal nitride to achieve superior reflectivity, and whose reflective surface does not participate in the wafer-bonding process directly.

Abstract: An LED structure is disclosed herein, which comprises, sequentially arranged in the following order, a light generating structure, a non-alloy ohmic contact layer, a metallic layer, and a substrate. As a reflecting mirror, the metallic layer is made of a pure metal or a metal nitride for achieving superior reflectivity. The non-alloy ohmic contact layer is interposed between the metallic layer and the light generating structure so as to achieve the required ohmic contact. To prevent the metallic layer from intermixing with the non-alloy ohmic contact layer and to maintain the flatness of the reflective surface of the first metallic layer, an optional dielectric layer is interposed between the metallic layer and the non-alloy ohmic contact layer.

Abstract: A material made by arranging layers of gallium-arsenide-antimonide (GaAsxSb1-x, 0.0?x?1.0) and/or indium-gallium-arsenic-nitride (InyGa1-yAszN1-z, 0.0?y, z?1.0) in a specific order is used to form the transistor base of a heterojunction bipolar transistor. By controlling the compositions of the materials indium-gallium-arsenic-nitride and gallium-arsenide-antimonide, and by changing the thickness and order of the layers, the new material would possess a specific energy gap, which in turn determines the base-emitter turn-on voltage of the heterojunction bipolar transistor.

Abstract: A method of manufacturing a light emitting diode (LED) includes growing a light emitting region on a temporary substrate, bonding a metal-coated reflective permanent substrate and then removing the temporary substrate. The reflective metal layer also serves as a bonding agent for bonding the permanent substrate. The bonded LED element and permanent substrate are heated in a wafer bonding tool that includes a graphite lower chamber and a graphite upper cover with a stainless steel screw. Because of the different thermal expansion coefficients between stainless and graphite, the stainless steel screw applies a pressure to the bonded structure during the heating process to assist the bonding of the permanent substrate.