Abstract: Phase selection circuit for selecting a phase from signal source generating a multi-phase clock signal is implemented utilizing a single stage of multiplexing gates for receiving taps from signal source, thus minimizing mismatch between phases. Multiplexing gates, connected together at their outputs, select between a tap and an inverse tap and are always left on. The outputs from multiplexing gates are analog summed together to create a single phase output signal which may be shifted in phase by one tap simply by inverting one of the input taps to a multiplexing gate, thus reducing glitching at output signal. Phase interpolation is provided for by further phase shifting the output in steps smaller than one tap utilizing multiplexor circuit which interpolates in multiple steps between a tap and inverse tap. Phase selection circuit provides for provides maximum bandwidth capability, while minimizing mismatch and glitching.

Abstract: The present invention provides a time delay system that generates a selectable asynchronous time delayed signal from an incoming signal using a pulse having a minimum pulse width and stop-startable oscillator. The time delay system of the present invention produces a minimum data dependency error which is independent of the repetition rate of the incoming signal, the substrate settling time, and the length of the time delay of the delayed signal.

Abstract: A phase interpolation voltage controlled oscillator (VCO). In one embodiment, the VCO is a multiple phase interpolation VCO. The multiple phase interpolation VCO includes a plurality of phase shifting cells each receiving an oscillating signal, and each phase shifting the oscillation signal a different amount. Summing cells receive the phase shifted oscillating signals and combine the signals to determine an output oscillating signal. In one embodiment, further summing cells receive the output of other summing cells to determine the output oscillating signal.

Abstract: A transimpedance amplifier in an optical communication system is provided with automatic gain control (AGC) for increasing the input operating range while maintaining high stability. A photodetector is used to convert an optical signal into a differential current for the transimpedance amplifier. An AGC circuit has a gain control device connected across the differential input of the transimpedance amplifier. The gain control device has an impedance that varies as a function of a voltage at the differential output of the transimpedance. Preferably, the gain control device is a FET having a drain coupled to one of the differential inputs, a source coupled to the other differential input, and a gate for receiving an AGC voltage, the AGC voltage being a function of the voltage at the differential output.

Abstract: A self-routing packet switching network architecture receives parallel incoming data packets and divides each of the corresponding bits within each data packet into words. The words are distributed into multiple transport channels, one word being placed into each channel in an alternating fashion. The words are transported through the channels and later words are input to the channels. Header words are also input to a self-routing network circuit. The self-routing network circuit determines the switching decisions to be made at each stage of a routing segment in order to properly route the words. Routing segments at the ends of the transport channels route the data according to these switching decisions. The use of multiple transport channels allows the network to operate internally at a reduced clock rate while still maintaining the same bandwidth as a direct bridge network architecture.

Abstract: An improved GaAs switching device is disclosed, of the type having a switched clamp which shunts pull-up current except during a portion of a "0" to "1" transistion at the device's output. The device herein provided enhanced immunity to interconnect resistance by isolating the gate-to-source Schottky diode of the clamp's FET from the device's output node. In accordance with the invention, the gate-to-source current through the clamp's FET is limited by an impedance device in the FET's gate circuit to provide the isolation.