Abstract: A differential amplifier circuit achieves offset cancellation by supplying an offset correction current from a current copier circuit to the output of the differential amplifier. The current copier is programmed by closing a first switch to short the differential input terminals of the amplifier, by opening a second switch to break the feedback loop of the amplifier, and by closing a third switch to allow the current copier to sense the offset output voltage at the output of the amplifier. The current copier generates an equal and opposite offset cancellation current which is summed with the offset current from the amplifier. The current copier circuit includes a storage capacitor for storing a voltage required to produce such offset cancellation current. After programming the storage capacitor, the third switch is opened, the first switch is opened, and the second switch is closed for normal operation.

Abstract: A column-driver integrated circuit, and related method, for driving the columns of LCD displays uses paired digital-to-analog converters to provide analog signals in an upper voltage range and in a lower voltage range. During a first drive cycle, first and second digital data words are provided to the first and second digital-to-analog converters; the first and second digital data words represent the magnitudes, within the upper voltage range and lower voltage range, respectively, of the analog signals to be driven onto first and second columns of the LCD display. The analog signal generated by the first D/A converter is selected, as by a multiplexer, onto the first column of the display, and the analog signal generated by the second D/A converter is selected onto the second column of the display.

Abstract: A power-saving column driver integrated circuit, and a power-saving method for driving a liquid crystal display, include a series of multiplexers coupled to the columns of the display. The multiplexers selectively couple each of the columns to a common external storage capacitor during a portion of each row drive period for discharging each of the pixels in the selected row of the liquid crystal display to a median bias voltage. During the remaining portion of each row drive period, the multiplexers selectively couple voltage drivers to the columns of the LCD pixel array for applying a desired driving voltage to each column of the array. The polarity of the driving voltages applied to each column alternates on succeeding row drive periods, and the resulting voltage that is summed on the storage capacitor averages to the median bias voltage.

Abstract: An integrated circuit assembly using tape automated bonding (TAB) reduces the number of TAB test pads formed upon the TAB film, for purposes of testing the integrated circuit prior to surface mounting, by sharing at least some of such test pads between at least two output terminals of the integrated circuit. A control signal indicates to the integrated circuit that a TAB test mode of operation is in effect. A second control signal indicates which of the two output signals should be enabled to the shared test pad during the TAB test mode. Multiplexers are provided at the output terminals, and are responsive to such control signals, for selectively allowing one of such output signals to be conducted to the test pad, while temporarily presenting a high impedance at the other output terminal. A method of testing such integrated circuit assembly includes the step of trimming such test pads from the tape automated bonding film after testing and before surface mounting.

Abstract: A column-driver integrated circuit, and related method, for driving the columns of LCD displays uses paired digital-to-analog converters to provide analog signals in an upper voltage range and in a lower voltage range. During a first drive cycle, first and second digital data words are provided to the first and second digital-to-analog converters; the first and second digital data words represent the magnitudes, within the upper voltage range and lower voltage range, respectively, of the analog signals to be driven onto first and second columns of the LCD display. The analog signal generated by the first D/A converter is selected, as by a multiplexer, onto the first column of the display, and the analog signal generated by the second D/A converter is selected onto the second column of the display.

Abstract: CMOS transistor logic circuitry is permitted to operate at higher power supply voltages while retaining lower voltage processing geometries by providing each input signal as dual input signals that track each other within two different voltage ranges. A shield voltage is provided approximately midway between the uppermost and lowermost power supply voltages. The first input signal ranges between the lowermost power supply voltage and the shield voltage, and the second input signal ranges between the shield voltage and the uppermost power supply voltage. The first and second input signals drive the gates of n-channel and p-channel CMOS switching transistors, respectively, the drain terminals of which are coupled to first and second output terminals, respectively. N-channel and p-channel shield transistors are connected in series between the first and second output terminals, and have their gate terminals coupled to the shield voltage.

Abstract: An integrated circuit for driving an active or passive matrix liquid crystal display panel or the like provides an analog output signal which switches through a voltage range that exceeds the safe operating voltage of the CMOS transistors from which it is formed. Duplicate digital to analog conversion circuits are provided on the integrated circuit but are operated from two different power supply voltage ranges. Each voltage range has a magnitude less than the safe operating voltage. The analog output signals generated by the duplicate digital to analog conversion circuits are coupled to an output multiplexer that is responsive to a control signal for selecting one of the two analog output signals to the output terminal of the integrated circuit.

Abstract: An integrated circuit is provided for generating analog output voltages for a series of column driver output circuits used to drive an active or passive matrix LCD display. The digital value corresponding to the shade of gray for each column is stored on the integrated circuit. A shift register is clocked to sequentially enable tap points of a resistive divider network for providing four monotonically increasing analog voltages on each shift register clock cycle. A binary counter is clocked along with the shift register, and the more significant bits of the stored digital value for each column driver output circuit are each compared with the current binary count to detect a correlation. Upon detecting a correlation, the two least significant bits of the stored digital value for each column driver circuit are used to select one of the four analog voltages during the current counter cycle, and the selected analog value is sampled and held for driving a column of the LCD display.

Abstract: A power-saving column driver integrated circuit, and a power-saving method for driving a liquid crystal display, include a series of multiplexers coupled to the columns of the display. The multiplexers selectively couple each of the columns to a common external storage capacitor during a portion of each row drive period for discharging each of the pixels in the selected row of the liquid crystal display to a median bias voltage. During the remaining portion of each row drive period, the multiplexers selectively couple voltage drivers to the columns of the LCD pixel array for applying a desired driving voltage to each column of the array. The polarity of the driving voltages applied to each column alternates on succeeding row drive periods, and the resulting voltage that is summed on the storage capacitor averages to the median bias voltage.

Abstract: An integrated circuit for driving an active or passive matrix liquid crystal display panel or the like provides an analog output signal which switches through a voltage range that exceeds the safe operating voltage of the CMOS transistors from which it is formed. Duplicate digital to analog conversion circuits are provided on the integrated circuit but are operated from two different power supply voltage ranges. Each voltage range has a magnitude less than the safe operating voltage. The analog output signals generated by the duplicate digital to analog conversion circuits are coupled to an output multiplexer that is responsive to a control signal for selecting one of the two analog output signals to the output terminal of the integrated circuit.

Abstract: CMOS transistor logic circuitry is permitted to operate at higher power supply voltages while retaining lower voltage processing geometries by inserting input shielding transistors before the gate terminals of each input switching transistor. Each shielding transistor has a gate terminal coupled to a shield voltage of a magnitude substantially midway between ground potential and the positive power supply voltage. The input signal is conveyed by the source-drain channel of the input shielding transistor to the gate of the switching transistor, while preventing the gate of the switching transistor from rising above the shield voltage, in the case of n-channel devices, or below the shield voltage, in the case of p-channel devices.