Abstract: A circuit arrangement utilizes a common bus for functional operations of logic circuits and for scan testing the logic circuits. In one embodiment, input/output ports and scan test ports of the logic circuits are switchably coupled to a bus. For functionally testing the logic circuits, a predetermined command transmitted over the bus causes the scan test ports to be coupled to the bus and the input/output ports to be decoupled from the bus. Test data may then be transmitted to and from the logic circuits via the bus. When testing is complete, a second predetermined command transmitted over the bus causes the scan test ports to be decoupled from the bus and the input/output ports to be coupled to the bus.

Abstract: A bridge circuit passes digital information between a primary PCI bus and a secondary PCI bus with increased throughput. The PCI busses carry digital information using respective clock signals having a known minimum skew therebetween. The interface bridge circuit includes primary and secondary PCI bus interfaces configured and arranged to communicate with the primary and secondary PCI busses respectively, and a memory buffer configured and arranged to store the digital information and to be accessed by the primary and secondary PCI bus interfaces. Further, a programmable configuration register is configurable in response to digital configure information received from the primary bus, and is adapted to provide an enable signal to one of the primary PCI bus interface and the secondary PCI bus interface. The enable signal indicates that the digital information is ready in the memory buffer for access by the one of the primary PCI bus interface and the secondary PCI bus interface.

Abstract: A method and apparatus for the alignment of a semiconductor device in preparation for patterning a layer of the device includes using an alignment apparatus which has one or more light sources for producing light at two or more alignment wavelengths. Typically, the semiconductor device will include alignment structures that are to be aligned with corresponding alignment markers on a photomask which contains the desired pattern. The alignment structures on the semiconductor device are often depressions or trenches in a layer of the device. The alignment apparatus determines the position of the alignment structures by observing the contrast in the intensity of light reflected off the region of the device containing the alignment structure and the region of the device adjacent to the alignment structure. This contrast in the intensity of light is wavelength dependent.

Abstract: A method for forming a scribe line on a semiconductor wafer including the steps of: (a) providing a semiconductor substrate; and (b) sequentially providing a plurality of layers over the semiconductor substrate of alternating conductive and insulating types, where each of the layers is provided with an elongated opening is formed relative to a desired scribe line position, and where the openings of at least some of the plurality of layers are wider than openings of preceding layers such that at least one sidewall of a completed scribe line has a pronounced slope extending outwardly from its base. The structure of the present invention is, therefore, a scribe line having sloped sidewalls that greatly reduces scribe line contamination problems and enhances planarization during subsequent spin-on-material processes. The scribe lines can either be elongated openings in the layers, or an elongated mesa formed in the layers.

Abstract: The asynchronous timing generator is comprised of a clock signal generator that generates a master clock signal. The master clock signal is used by a master clock counter to generate a bit clock. The master clock counter divides the master clock signal's frequency down to a lower frequency. Control signal information is extracted from the data stream's slot-framing to control the use of a predefined count value to a variable counter. The variable counter uses this lower frequency clock signal to generate the sub-bit count clock signal and slot bit numbers. These signals are generated in response to the control signals, coupled to the timer, indicating the different fields of the slot used to resynchronize data recovery in the received stream. In a preferred embodiment, the asynchronous timing generator is used in a communications transceiver device to permit resynchronization of received communications data.

Abstract: A phase-frequency detector for a phase-locked loop (PLL) circuit has symmetrical phase detection characteristics and produces symmetrical activation times on the "up" and "down" outputs for connection to a PLL charge pump circuit. The symmetrical characteristics are accomplished by using RS latch circuits at the outputs of the phase-frequency detector to provide the same loads and the same propagation delay for both the "up" and the "down" outputs. In addition, cross-wired sequential gates are used for at least some of the gates in the logic gate array of the detector to produce the same propagation delays in the gates.

Abstract: An integrated circuit test apparatus employs a main test circuit load board which has a circular array of relay card mounts located on it. Auxiliary relays, operated in conjunction with the load board, are mounted in groups on individual relay circuit cards, each card including several relays. The relay circuit cards have connectors on first and second edges thereof; and the connectors on the first edges interconnect with the corresponding receptacles on the relay card mounts. A customized configuration board load ring for the particular integrated circuit device under test (DUT) then is placed over the second edges of the relay circuit cards to interconnect with spring-loaded connectors on these edges to effect the configuration for the operation of the particular DUT which is undergoing test at any given time.

Abstract: A cache memory system operates without requiring valid bits in the external cache tag RAM by employing a system controller as a writeback cache controller for control of the cache data/tag memory and the system main memory. The system controller receives signaling information from a CPU through a host bus to indicate when to pre-load the cache memory or to flush (disable) the cache memory while maintaining memory coherencey by causing the cache controller to write back all modified lines in the cache memory to the main memory.

Abstract: A joystick system is designed to provide a modified digital representation of the setting of a joystick potentiometer. The system operates to compensate for non-linearities and offsets in the joystick response, or may be used to enhance or vary the joystick response to a non-linear form. This is accomplished by supplying the output voltage of the joystick to an analog-to-digital converter, the output of which then is supplied to a lookup table. The lookup table output is provided to a counter. In one mode of operation, the counter counts down to zero at some multiple of a sample rate. When the counter reaches a zero count, the time interval representative of the joystick position is indicated; and the corrected or enhanced position is indicated by this output.

Abstract: The ball bump structure of the subject invention provides a hermetically sealed bond pad at the surface of a semiconductor chip. An adhesion pad is formed at the surface of the bond pad. The adhesion pad includes a barrier layer, preferably a titanium/tungsten alloy, and a bonding layer, for example, a sputtered gold layer. A gold ball bump is formed on the adhesion pad. Methods for forming the improved structure herein are also disclosed.