Patents Assigned to VLSI Techology, Inc.
  • Patent number: 5434098
    Abstract: The present invention relates to a double poly MOS structure and a method for polysilicon capacitor formation which allows for independent adjustment of an interpoly oxide layer without affecting thickness of the gate oxide layer. In an exemplary embodiment, a first oxide layer is formed above a polysilicon layer. A second oxide layer is subsequently formed on the substrate to establish a gate oxide in an active area of the transistor. As a result, the interpoly oxide layer is formed by a combination of the first and second oxide formations, while the gate oxide layer is formed by only the second oxide formation. Thus, the thickness of the interpoly oxide layer can be adjusted by increasing or decreasing the thickness of the first oxide formation without changing the thickness of the gate oxide layer.
    Type: Grant
    Filed: June 3, 1994
    Date of Patent: July 18, 1995
    Assignee: VLSI Techology, Inc.
    Inventor: Kuang-Yeh Chang
  • Patent number: 4852038
    Abstract: A calculating apparatus receives four operands ("a, b, c and d") simultaneously. A first multiplier/divider performs the calculation of a*b or a.div.b and provides an output u. A second multiplier/divider performs the calculation of c*d or c.div.d and provides an output v. An adder/subtractor receives u and v and performed the calculation of u+v and u-v. A controller controls the operation of the first and second multiplier/divider to select the operation of multiplication or division.
    Type: Grant
    Filed: July 2, 1985
    Date of Patent: July 25, 1989
    Assignee: VLSI Techology, Inc.
    Inventors: Lawrence F. Wagner, Wayne P. Burleson, Korbin S. Van Dyke