Abstract: An integrated circuit device including a FIFO and a clock generator having a pulse swallower. The pulse swallower eliminates pulses from a reference frequency signal, producing a primary digital transceiver clock signal having a frequency of chiprate(S)(n), which is used to clock a digital transceiver when the device is in a primary mode. A first clock divider divides the frequency of the primary digital transceiver clock signal to produce a FIFO output clock signal having a frequency of chiprate(S). The FIFO has a data bus input for coupling to a data output, for example from an analog transceiver. The FIFO also has an external clock input for coupling to a clock output, for example from the analog transceiver. The external clock signal clocks the data into the FIFO asynchronous with the primary digital transceiver clock signal at a frequency of chiprate(S). The internal clock signal clocks the data out of the FIFO, synchronous with the primary digital transceiver clock signal at a frequency of chiprate(S).

Abstract: A slurry dispensing carrier ring for confining a semiconductor wafer to a polishing pad in a chemical mechanical polishing machine. The slurry dispensing ring has a diameter and a lower surface substantially parallel to the plane defined by the diameter and an inner radius surface substantially orthogonal to the plane defined by the diameter. The inner radius surface is adapted to confine the semiconductor wafer. An outer radius surface is located opposite the inner radius surface. An upper surface is located opposite the lower surface. A slurry dispense hole extends through the carrier ring from the upper surface to the lower surface, wherein the slurry dispense hole is adapted to flow a slurry used for chemical mechanical polishing from the chemical mechanical polishing machine to the lower surface so that the slurry contacts the semiconductor wafer confined within the inner radius surface.

Abstract: A multiprocessor system comprises a series of processors arranged to process data in an assembly-line fashion. Each processor includes an executor (execution unit, instruction decoder, and program counter) and a set of registers. Each set of registers is divided into two banks. At any given time, one bank is the “active” bank that is accessible by the local processor, and the other is the “shadow” bank, inaccessible to the local processor. Each processor but the last writes in parallel to its active bank and to the shadow bank of the immediate downstream processor. When all processors have completed working the data in their respective possession, a context-switch is performed switching register banks so that former active banks become shadow banks and former shadow banks become active banks. This makes data that was being processed by an upstream processor virtually immediately available to a local processor.

Abstract: A test device and method for determining parameters of a plurality of vias formed into a dielectric material making contact to a buried conductive layer. The present invention is comprised of a sample structure disposed within the material through which a plurality of vias are to be formed. The sample structure is adapted to enhance secondary electron yield from the via bottom during a scanning electron microscope examination of the vias. Additionally, the plurality of vias to be formed are disposed intentionally offset with respect to the sample structure. As a result, the enhanced secondary electron yield from the sample structure characterizes the degree of misalignment present in the via formation process. In so doing, the present invention simultaneously quantifies the critical dimension of the vias, the alignment/registration of the via formation process, and determines whether or not the vias are etched to a minimum desired depth.

Abstract: A circuit arrangement for interconnecting electronic components such as integrated circuit devices, chip packages and/or circuit boards includes signal, first fixed potential (e.g., power) and second fixed potential (e.g., ground) interconnects arranged into an interconnection layout pattern that offers greater flexibility, performance and cost effectiveness than conventional patterns. In some implementations, the interconnection layout pattern incorporates one or more tiles of interconnects, with each tile defining a plurality of interconnect positions arranged into at least three rows and at least four columns. For each tile, a signal interconnect is disposed at each of the three interconnect positions in each of the first and fourth columns, and one each of a signal interconnect, a first fixed potential interconnect and a second fixed potential interconnect are disposed in each of the second and third columns.

Abstract: The present invention relates to multilevel integrated circuit interconnection techniques. An integrated circuit having a number of electronic components along a semiconductor substrate and a first connection layer having a first number of conductors in selective electrical contact with the components is provided. A first insulative layer is formed on the first connection layer with a first pattern of openings therethrough. A second connection layer is established that has a second number of conductors selectively interconnected to the first conductors through the first pattern of openings. A second insulative layer is formed on the first connection layer with a second pattern of openings therethrough. A third connection layer is formed on the second insulative layer having a third dielectric and a third number of conductors selectively interconnecting the second conductors.

Abstract: The present invention is a conditioning ring for conditioning a polishing pad in a chemical-mechanical polishing machine. The conditioning ring is comprised of a ring having a diameter and a conditioning surface substantially parallel to a plane defined by the diameter. The conditioning ring has an inner radius surface to the plane defined by the diameter, wherein the inner radius surface is adapted to accept a wafer. The conditioning ring has an outer radius surface opposite the inner radius surface and an upper surface opposite the conditioning surface. The chemical mechanical polishing machine polishes the wafer by moving the polishing pad with respect to the wafer while the wafer is in contact with the polishing pad. The conditioning surface is adapted to frictionally contact the polishing pad.

Abstract: A method of and a system for allowing cacheable system memory to be accessed in a non-cacheable manner. In one embodiment of the present invention, a computer system is tricked during POST (Power-On Self-Test) to reserve a first region in a non-cacheable address space for a virtual peripheral device. The computer system is then tricked during operating system startup to reserve a second region in a cacheable address space. In the present embodiment, the first region is then mapped to the second region such that accesses to the first region is automatically forwarded to the second region. As a result, objectives of the present invention are achieved as cacheable memory may be accessed via accessing non-cacheable memory of the computer system.

Abstract: A programmed design tool and method for determining the placement of components of a very large scale integrated circuit. The present invention is characterized by a common timing engine adapted to check front end high level timing constraints in relation to a netlist representing the circuit.

Abstract: A method and system that enables a wireless repeater within the personal handy phone system to switch the communication mode of each slot within its communication interface. Specifically, the repeater is able to function as a cell station while communicating with a portable station and function as a portable station while communicating with a cell station. For instance, when the repeater communicates with a cell station, it switches the communication mode of a desired slot within its communication interface into portable station communication mode. Conversely, when the repeater communicates with a portable station, it switches a desired slot within its communication interface into cell station communication mode. Since a repeater implemented with the present invention is able to switch the communication mode of each slot within its communication interface, the amount of internal circuitry required within the repeater is significantly reduced.

Abstract: A method and a system allocate a budget to a circuit design. A timing analysis is prepared for a circuit and a budget is automatically allocated to each of the blocks of the circuit.

Abstract: A differential true single phase latch and flip-flop designed to embody logic functions is described. The logic function embodied latch includes a first circuit branch including first input switching devices for receiving a first set of input signals which include input signals and their corresponding complements and for outputting a first output signal having a logic state representative of the results of a logic function performed on said first set of input signals and a second circuit branch including second input switching devices for receiving the complement of the at least two input signals and can include the at least two input signals and for outputting a non-inverted output signal. First and second input switching devices are configured so as to cause the latch to perform logic functions on the input signals and latch output states corresponding to the results logic functions on its non-inverted and inverted outputs in the same clock phase.

Abstract: A circuit on a detachable device, such as a plug-in card, determines when the detachable device has been disconnected from a host device. The circuit includes a node, a power source, a switch and a control circuit. The node is connected to ground when the detachable device is connected to the host device. The node is disconnected from ground when the detachable device is disconnected from the host device. The switch is for connecting and disconnecting the node to the power source. The control circuit is for, repeatedly at a predetermined interval of time while the detachable device remains connected to the host device, causing the switch to connect the node to the power source for a first length of time. The control circuit, at the end of the first length of time, checks a voltage level of the node in order to detect whether the detachable device has been disconnected from the host device.

Abstract: Semiconductor wafer processing methods are described. In one implementation, a semiconductor wafer is provided with a layer of photoresist thereover. A matrix is defined within the photoresist and comprises a plurality of exposed grating patterns which are formed through successive exposure passes of a mask which defines the grating pattern. The wafer is exposed to conditions which are effective to remove at least some of the photoresist and to clear substantially all of the photoresist over a wafer portion underlying at least one of the exposed grating patterns. The wafer is inspected and at least one processing parameter associated with photoresist which was removed during processing can be ascertained. In a preferred aspect, the processing parameter comprises an illumination exposure dosage. In a preferred implementation, two exposure passes with the mask are made with a second of the passes being shifted by a predetermined amount relative to the grating pattern defined by the first pass.

Abstract: The present invention discloses a method and an apparatus for making digital integrated circuits by considering ramp delay and clock skew as constraints while minimizing the number of inserted buffers and overall wire length connecting components for large clock trees. The invention includes developing a set of circuit specifications including maximum clock skew, minimum driveability, and maximum ramp delay. These specifications are described in a hardware description language on a digital computer system, and a netlist is synthesized from this hardware description. A modified netlist is then formed by analyzing the netlist and inserting buffers into it to satisfy the circuit specifications of skew, driveability, and ramp delay. Thereafter, a digital integrated circuit is produced as specified by the modified netlist.

Abstract: A method and system for measuring the thickness of a patterned film. In one embodiment, a first patterned film is impinged with electromagnetic radiation having a wavelength which varies within a given wavelength range. The electromagnetic radiation reflected from the first patterned film is measured. The thickness of the first patterned film is then measured using thickness measuring equipment. The determined thickness of the first patterned film is then correlated with the measured reflectance of the electromagnetic radiation from the first patterned film. A second patterned film is then impinged with electromagnetic radiation having a wavelength which varies within the given wavelength range. The electromagnetic radiation reflected from the second patterned film is measured. The present invention uses the previously determined correlation to determine the thickness of the second patterned film.

Abstract: In a method of designing cells applicable to different first and second design automation systems, first and second cells circuit-designed by the first and second design automation systems, respectively, are demarcated into a logic function portion and an input/output portion. A plurality of sets of common lithography patterns for the logic function portions of the first and second cells are determined such that each common lithography pattern set is shared by those of the first and second cells which have same logic function in the first and second design automation systems. A first set of lithography patterns for the input/output portions of the first cells in the first design automation system and a second set of lithography patterns for the input/output portions of the second cells in the second design automation system are determined, respectively.