Abstract: A processor comprising a control unit and a plurality of processing units interacting according to an operating architecture imposed dynamically by the control unit from among at least two of the following architectures: a single instruction multiple data (SIMD) stream architecture, a multiple instruction single data (MISD) stream architecture, and a multiple instruction multiple data (MIMD) stream architecture. The operating architecture is imposed dynamically by the control unit according to: configuration functions included in a machine code, and/or data to be processed and current processing instructions received as input of the processor.

Abstract: A processor comprising a control unit and a plurality of processing units interacting according to an operating architecture imposed dynamically by the control unit from among at least two of the following architectures: a single instruction multiple data (SIMD) stream architecture, a multiple instruction single data (MISD) stream architecture, and a multiple instruction multiple data (MIMD) stream architecture. The operating architecture is imposed dynamically by the control unit according to: configuration functions included in a machine code, and/or data to be processed and current processing instructions received as input of the processor.

Abstract: A computing device comprising: a plurality of ALUs; a set of registers; a memory; a memory interface between the registers and the memory; a control unit controlling the ALUs by generating: at least one cycle i including both implementing at least one first computing operation by way of an arithmetic logic unit and downloading a first dataset from the memory to at least one register; at least one cycle ii, following the at least one cycle i, including implementing a second computing operation by way of an arithmetic logic unit, for which second computing operation at least part of the first dataset forms at least one operand.

Abstract: A method for data processing implemented by computer means and comprises: for a plurality of objects of the data processing, conducting an analysis of a computer code of the data processing defining a use of said objects in the data processing, on the basis of the analysis of the computer code (COD), allocating each object to one of a plurality of memory areas for the construction and then the destruction of each object in the corresponding memory area during the data processing, in such a way that, during the data processing, each memory area exhibits stack operation.