Patents Assigned to VSYNC Circuit, Ltd.
  • Static analysis of VLSI reliability
    Patent number: 8707229
    Abstract: A circuit verifier having an input interface configured to receive descriptions of integrated circuits and a processing unit configured to scan through a description of an integrated circuit received through the input interface in order to identify clock domain crossings in the circuit and to provide a numerical score for each of the identified clock domain crossings.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: April 22, 2014
    Assignee: VSYNC Circuit, Ltd.
    Inventors: Rostislav (Reuven) Dobkin, Leonid Brook