Patents Assigned to VSYNC Circuits Ltd.
  • Static analysis of VLSI reliability
    Patent number: 8707229
    Abstract: A circuit verifier having an input interface configured to receive descriptions of integrated circuits and a processing unit configured to scan through a description of an integrated circuit received through the input interface in order to identify clock domain crossings in the circuit and to provide a numerical score for each of the identified clock domain crossings.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: April 22, 2014
    Assignee: VSYNC Circuit, Ltd.
    Inventors: Rostislav (Reuven) Dobkin, Leonid Brook
  • VLSI black-box verification
    Patent number: 8661383
    Abstract: A circuit verifier scans through a description of an integrated circuit to identify black-boxes in the description. The verifier assigns the identified black-boxes to clock domains and identifies clock domain crossings, in which a black-box assigned to a first clock domain is connected to an element belonging to a second clock domain. In some cases the verifier identifies signal reconvergence through black-boxes.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: February 25, 2014
    Assignee: VSYNC Circuits, Ltd.
    Inventors: Rostislav (Reuven) Dobkin, Leonid Brook
  • Constraining VLSI circuits
    Patent number: 8631364
    Abstract: A method of circuit design performed in which a description of a multi-clock-domain circuit is analyzed to locate clock domain crossings. A processor automatically identifies, for at least one of the located clock domain crossings, one or more elements of a synchronization circuit of the clock domain crossing, which require constraining. The processor then generates a constraint for implementation of the identified one or more elements in a design of the circuit.
    Type: Grant
    Filed: December 26, 2011
    Date of Patent: January 14, 2014
    Assignee: VSYNC Circuits Ltd.
    Inventors: Rostislav (Reuven) Dobkin, Leonid Brook