Abstract: A configurable device uses a plurality of parallel units which are made up of cells for storing individual bits of information. These cells are identified by address signals and selected to be interrogated. The selected cells are interrogated to determine information stored therein and a signal is produced which corresponds to that information. If a nonfunctional cell is detected within a parallel unit, that parallel unit may be decoupled from the interrogator. The remainder of the parallel units are shifted to different interrogators thereby effectively eliminating use of the decoupled parallel unit which contains the nonfunctional cell.

Abstract: A timing synchronizing circuit with a phase locked loop. A multiplexor is employed to cause the phase locked loop to alternate between a self-excited mode for maintaining the frequency of a recovered timing signal and a mode in which state transitions of a baseband data signal are compared with the phase locked loop feedback signal to adjust the frequency of the recovered timing signal.

Abstract: A differential charge pump for use in a phase locked loop. The charge pump generates a voltage difference signal proportional to the duration of first and second pulse trains provided by a phase comparator. The charge pump includes a differential amplifier for generating the difference signal, first and second RC filter networks connected between the noninverting and inverting terminals of the differential amplifier and a reference node, respectively. Parallel, all-NPN switching networks apply charging current pulses to the first RC filter network in response to the first pulse train and they apply charging current pulses to the second RC filter network in response to the second pulse train.

Abstract: A junction field effect transistor fabricated by a simplified process for incorporation into an integrated circuit including bipolar transistors is disclosed. The JFET comprises an isolated gate region of a first conductivity type with a surface on the integrated circuit and a buried layer beneath the surface to enhance conductivity. A pair of spaced-apart regions of a second conductivity type extend into the gate region form the surface but not into contact with the buried layer. A plurality of ion implanted subsurface channels of the second conductivity type extend between the pair of spaced-apart regions. Between each subsurface channel and the surface is an upper gate region of the first conductivity type, each of which has an enhanced dopant concentration compared with adjacent portions of the gate region. The upper gates are formed through the same mask as the subsurface channels for insuring optimal alignment of the gates with the channels and simplifying fabrication.

Abstract: A lightly doped drain in an IGFET is provided by fabricating the transistor in a epitaxial layer lightly doped in the conductivity type of the channel for the device. The laterally reduced dopant concentration of the drain, and a lightly doped source if desired, is provided by leaving portions of the epitaxial layer unmodified.

Abstract: A delay circuit for differential signals has input terminals for receiving primary and complementary phases of the differential signals and output terminals upon which the primary and complementary phases of output differential signals are generated after a suitable delay. A differential comparator controls charging and discharging of first and second capacitors, one capacitor being provided for each phase for providing a seleced delay. The time difference between switching of the differential comparator and the subsequent voltage level transistion of the relative charges on the first and second capacitors determines the time delay dt. The delay circuit is compensated for power supply and temperature variation.

Abstract: A CMOS output buffer interconnects binary logic integrated circuits. The output buffer is readily configurable through variation of a single metallization mask during fabrication for providing interconnection of integrated circuits through either transmission lines or lumped loads. The CMOS output buffer provides a pull-up circuit for pulling an output terminal to a voltage level corresponding to a first logical state and a pull-down circuit for pulling the output terminal to the complementary logical state. The pull-up and pull-down circuits each include a plurality of parallel connectable output drivers. A selected number of output drivers can be connected to the output terminal during fabrication of the integrated circuit through the appropriate metallization mask. The pull-up and pull-down circuits each include a distributed, continuous control electrode providing for delayed propagation of actuation signals.

Abstract: The present invention is a method for packaging and protecting an integrated circuit chip on a carrier tape. A carrier tape comprising at least two bonded layers (one layer being made of an electrically conductive material) includes small flat leads in the conductive layer. A carrier bridge or frame of nonconductive material is bonded to one surface of the leads and is connected to a nonconductive layer (or a part of) the tape. The electrical pads of an integrated circuit are bonded to the respective leads of the tape simultaneously. The leads are cut at a predetermined length from the chip and outside of the frame. The lead ends are bent to form a nest. A planar base is adhered to the surface of the chip having the electrical pads. The leads are then bent over the base to secure the base on the tape and provide electrical contact points to the chip. The chip is coated with a suitable material and to provide insulation and encapsulation of the entire packaging structure.

Abstract: A skew compensated RS422 buffer includes a skew compensation circuit and an output driver. The output driver is connected to receive a complementary pair of compensated drive signals, and provides complementary buffer output signals in response thereto. Due to asymmetric switching characteristics, buffer output signals in response to falling edge drive signals are delayed by an inherent skew period with respect to buffer output signals in response to rising edge drive signals. The skew compensation circuit includes a NOR gate and an AND gate, both of which have a first input terminal connected to receive buffer input signals. The buffer input signals are also applied to second input terminals of both the NOR gate and AND gate through delay gates which delay signal propagation by delay periods substantially equal to the inherent skew period of the output driver.

Abstract: A single chip monolithic integrated successive approximation analog-to-digital converter includes a test mode terminal for receiving shift register test mode control signals and successive approximation mode control signals. Digital test data signals are applied to a test data terminal. A trimmable digital-to-analog converter (DAC) is connected to receive digital signals and converts these signals to analog signals of corresponding values. A successive approximation and shift register is coupled to the test mode terminal and the test data terminal. During post-fabrication processing, the successive approximation and shift register operates in a shift register test mode in response to the test mode control signals. Test signals of a known value are serially received and applied in parallel to the DAC. The DAC can then be trimmed to required specifications. The successive approximation and shift register operates in a successive approximation mode in response to successive approximation mode control signals.

Abstract: An integrated, high speed, zero hold current and delay compensated charge pump operable at one of two different selectable pumping currents. The charge pump includes first and second supply terminals, a first input terminal for receiving digital charge-up control signals, a second input terminal for receiving digital charge-down control signals, and an output terminal. A first transistorized differential amplifier controls a first current flow of a first polarity between the first supply terminal and the output terminal as a function of the charge-up control signals. A second differential amplifier controls a second current flow between the first and second supply terminals as a function of the charge-down control signals. A pump current mirror produces a mirrored second current flow of a second polarity between the output terminal and the second supply terminal as a function of the second current flow.

Abstract: A bias current cancellation circuit provides current to the bases of a pair of transistors forming a differential amplifier. A transistor of matched characteristics to the differential amplifier pair is operated so that its base current replicates the base currents of the differential transistor pair. This replicated base current is inverted by a current mirror which is connected to the bases of the differential transistional pair. A second order cancellation error caused by base current differences in the current mirror is cancelled by a feedback circuit so that only the base current of the matching transistor affects the currents supplied to differential amplifier.

Abstract: Trimming of input offset voltage of a diferential amplifier is provided by a pair of resistance networks which are connected to the emitters of a pair of current mirror transistors. By adjusting the resistances of the resistance networks, the adjustment currents flowing through the current mirror transistors are selected to cancel out the input offset voltage of the differential amplifier. Each resistance network includes a plurality of resistors connected in series with a low resistance shorting link connected in parallel with each of the plurality of resistances. The input offset voltage is trimmed by selectively cutting the shorting links with a two-phase measure and trim process.

Abstract: The present invention provides a method for protecting integrated circuit packages mounted on carrier tapes during manufacturing steps commonly employed in tape automated bonding processes. A reel is provided for winding the carrier tape into a compact package. A steel tape with corrugated longitudinal edges is also provided for winding on the reel in alternating layers with the carrier tape. The carrier tape thus is framed, layer by layer, with the steel tape, thus protecting each integrated circuit package from coming into contact with another object during manufacturing steps, e.g. heat curing.

Abstract: A resistor network coupling two terminal leads and adapted to be fabricated on an integrated circuit. A plurality of N-sided meshes are each formed by N resistor elements linked at network nodes. Some of the resistor elements can be cut by a laser under computer control to select a desired resistance value of the network.

Abstract: An apparatus for electrically and thermally "burning in" a plurality of integrated circuits mounted on a carrier tape includes a printed circuit board base and a cover. The printed circuit board base includes a plurality of contact arrays arranged and constructed to contact the leads from the integrated cirucits mounted on the tape. The cover is pivotally connected to the printed circuit board base and includes a corresponding number of pressure pads which force contact between integrated circuit leads and a contact array when the cover is in its closed position. A locking assembly is provided to keep the cover locked in its closed position. The printed circuit board base also carries circuitry for electrically exercising the integrated circuits during burn-in.

Abstract: An amplifier output stage includes current limiting circuitry for limiting the current in the output stage if the output terminal is shorted to ground. The current sinking and the current sourcing output transistors each have a current limiting circuit which mirrors the collector current of the output transistor, produces a voltage which is a function of the mirrored collector current, and controls base current to the output transistor as a function of the voltage. The output current limiting function, therefore, is provided without sacrificing output voltage swing of the output stage.

Abstract: A bipolar integrated circuit amplifier with a cascode stage has an emitter follower biasing circuit which provides a bias voltage to the cascode stage. The cascode amplifier stage is stabilized by providing a stabilization capacitance across the base-collector junction of the emitter follower in the biasing circuit.

Abstract: An apparatus for electrically and thermally "burning in" a plurality of integrated circuits mounted on a carrier tape includes a printed circuit board base and a pair of covers. The printed circuit board base includes a plurality of contact arrays arranged and constructed to contact the leads from the integrated circuits mounted on the tape. The pair of covers are pivotally connected to the printed circuit board base. The covers include a corresponding number of pressure pads which force contact between integrated circuit leads and a contact array when a cover is in its closed position. A locking assembly is provided to keep the covers locked in their closed positions. The printed circuit board base also carries circuitry for electrically exercising the integrated circuits during burn-in.

Abstract: The present invention is a method for packaging and protecting an integrated circuit chip on a carrier tape. A carrier tape comprising at least two bonded layers (one layer being made of an electrically conductive material) includes small flat leads in the conductive layer. A carrier bridge or frame of nonconductive material is bonded to one surface of the leads and is connected to a nonconductive layer (or a part of) the tape. The electrical pads of an integrated circuit are bonded to the respective leads of the tape simultaneously. The leads are cut at a predetermined length from the chip and outside of the frame. The lead ends are bent to form a nest. A planar base is adehered to the surface of the chip having the electrical pads. The leads are then bent over the base to secure the base on the tape and provide electrical contact points to the chip. The chip is coated with a suitable material and to provide insulation and encapsulation of the entire packaging structure.