Abstract: A system and method for presenting information related to an operation of a chip may include obtaining an input file including entries that record an operation of a chip; based on at least one parameter, identifying at least one pattern of entries in the input file; and based on analyzing a plurality of occurrences of the pattern, selecting an occurrence of the pattern that records a root cause of a problem.
Abstract: A graphical tool creates design-verification environments. The tool includes a graphical environment builder that allows for the drag and drop addition of verification IP (“VIP”) modules to a graphical verification environment. The tool assigns connector signals associated with source code that simulates a connection between a VIP module and the device under test (“DUT”). The tool learns which connection signals are suitable to connect a VIP to the DUT and facilitates selecting of the suitable signals in the environment development process. The tool converts the graphical environment to source code that can be executed to simulate testing on the DUT. The tool also allows a user to navigate between view modes that display the verification environment graphically, and that display the source code associated with components of the verification environment.
Abstract: A graphical tool creates design-verification environments. The tool includes a graphical environment builder that allows for the drag and drop addition of verification IP (“VIP”) modules to a graphical verification environment. The tool assigns connector signals associated with source code that simulates a connection between a VIP module and the device under test (“DUT”). The tool learns which connection signals are suitable to connect a VIP to the DUT and facilitates selecting of the suitable signals in the environment development process. The tool converts the graphical environment to source code that can be executed to simulate testing on the DUT. The tool also allows a user to navigate between view modes that display the verification environment graphically, and that display the source code associated with components of the verification environment.
Abstract: A graphical tool creates design-verification environments. The tool includes a graphical environment builder that allows for the drag and drop addition of verification IP (“VIP”) modules to a graphical verification environment. The tool assigns connector signals associated with source code that simulates a connection between a VIP module and the device under test (“DUT”). The tool learns which connection signals are suitable to connect a VIP to the DUT and facilitates selecting of the suitable signals in the environment development process. The tool converts the graphical environment to source code that can be executed to simulate testing on the DUT. The tool also allows a user to navigate between view modes that display the verification environment graphically, and that display the source code associated with components of the verification environment.
Abstract: A graphical tool creates design-verification environments. The tool includes a graphical environment builder that allows for the drag and drop addition of verification IP (“VIP”) modules to a graphical verification environment. The tool assigns connector signals associated with source code that simulates a connection between a VIP module and the device under test (“DUT”). The tool learns which connection signals are suitable to connect a VIP to the DUT and facilitates selecting of the suitable signals in the environment development process. The tool converts the graphical environment to source code that can be executed to simulate testing on the DUT. The tool also allows a user to navigate between view modes that display the verification environment graphically, and that display the source code associated with components of the verification environment.