Patents Assigned to Wafer-Level Packaging Portfolio LLC
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Publication number: 20130137259Abstract: A process for producing electrical contact connections for a component integrated in a substrate material is provided, the substrate material having a first surface region, and at least one terminal contact being arranged at least partially in the first surface region for each component, which is distinguished in particular by application of a covering to the first surface region and production of at least one contact passage which, in the substrate material, runs transversely with respect to the first surface region, in which process, in order to form at least one contact location in a second surface region which is to be provided, at least one electrical contact connection from the contact location to at least one of the terminal contacts is produced via the respective contact passages.Type: ApplicationFiled: January 8, 2013Publication date: May 30, 2013Applicant: WAFER-LEVEL PACKAGING PORTFOLIO LLCInventors: Florian Bieck, Jeurgen Leib
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Patent number: 8420445Abstract: A method for packing semiconductor components is provided, in which a first side of a first wafer is connected to at least one further wafer, wherein at least one of the wafers has a plurality a semiconductor circuits and wherein trenches are made in the second side of the first wafer opposite to the first side and divide the first wafer into a plurality of parts, which are separated from one another by the trenches, but are connected mechanically to one another by means of the at least one further wafer, and wherein the connecting region between the first wafer and the at least one further wafer has been or will be laterally exposed in the trenches. A coating that covers the connecting region is then applied to the regions of the trenches in which the connecting region is exposed.Type: GrantFiled: June 4, 2008Date of Patent: April 16, 2013Assignee: Wafer-Level Packaging Portfolio LLCInventor: Juergen Leib
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Patent number: 8399293Abstract: The present invention relates to the field of electronic devices and their associated driver and/or controller integrated circuits and in particular to the mechanical packaging of electronic devices and to the packaging of electronic devices and their associated driver and/or controller integrated circuits.Type: GrantFiled: September 13, 2011Date of Patent: March 19, 2013Assignee: Wafer-Level Packaging Portfolio LLCInventors: Juergen Leib, Hidefumi Yamamoto
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Patent number: 8349707Abstract: A process for producing electrical contact connections for a component integrated in a substrate material is provided, the substrate material having a first surface region, and at least one terminal contact being arranged at least partially in the first surface region for each component, which is distinguished in particular by application of a covering to the first surface region and production of at least one contact passage which, in the substrate material, runs transversely with respect to the first surface region, in which process, in order to form at least one contact location in a second surface region which is to be provided, at least one electrical contact connection from the contact location to at least one of the terminal contacts is produced via the respective contact passages.Type: GrantFiled: September 30, 2010Date of Patent: January 8, 2013Assignee: Wafer-Level Packaging Portfolio LLCInventors: Dipl.-Ing. Florian Bieck, Jürgen Leib
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Patent number: 8309384Abstract: A wafer level packaging process for packaging components is provided. The process includes permanently connecting a functional side of a base substrate to a covering substrate at wafer level so that a plurality of functional regions on the functional side are in each case packaged to form a wafer level package, the plurality of functional regions being spaced apart from one another on the functional side; producing contact-connection recesses in the base substrate to uncover contact surfaces on the base substrate from a back surface of the base substrate; dividing the base substrate into body regions and connection regions; thinning the body regions or the connection regions until the wafer level package has different thicknesses in the body regions and the connection regions; and dicing wafer level package into chips along predefined cutting lines between the plurality of functional regions.Type: GrantFiled: April 2, 2010Date of Patent: November 13, 2012Assignee: Wafer-Level Packaging Portfolio LLCInventor: Juergen Leib
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Patent number: 8114304Abstract: In order to achieve an integration of functional structures into the housing of electronic components, provision is made of a method for producing an electronic component comprising at least one semiconductor element having at least one sensor-technologically active and/or emitting device on at least one side, the method comprising the following steps: provision of at least one die on a wafer, production of at least one patterned support having at least one structure which is functional for the sensor-technologically active and/or emitting device, joining together of the wafer with the at least one support, so that that side of the die which has the sensor-technologically active and/or emitting device faces the support, separation of the die.Type: GrantFiled: November 22, 2006Date of Patent: February 14, 2012Assignee: Wafer-Level Packaging Portfolio LLCInventors: Jürgen Leib, Florian Bieck
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Publication number: 20120003791Abstract: The present invention relates to the field of electronic devices and their associated driver and/or controller integrated circuits and in particular to the mechanical packaging of electronic devices and to the packaging of electronic devices and their associated driver and/or controller integrated circuits.Type: ApplicationFiled: September 13, 2011Publication date: January 5, 2012Applicant: WAFER-LEVEL PACKAGING PORTFOLIO LLCInventors: Juergen Leib, Hidefumi Yamamoto
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Patent number: 8017435Abstract: The present invention relates to the field of electronic devices and their associated driver and/or controller integrated circuits and in particular to the mechanical packaging of electronic devices and to the packaging of electronic devices and their associated driver and/or controller integrated circuits.Type: GrantFiled: June 1, 2007Date of Patent: September 13, 2011Assignee: Wafer-Level Packaging Portfolio LLCInventors: Juergen Leib, Hidefumi Yamamoto
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Publication number: 20110169171Abstract: A chip package transmitting slow speed signals via edge connectors and high speed signals by means of through-silicon-vias. The edge connectors are formed in recesses formed in the sidewalls of the package.Type: ApplicationFiled: March 18, 2011Publication date: July 14, 2011Applicant: WAFER-LEVEL PACKAGING PORTFOLIO LLCInventor: Phil P. Marcoux
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Patent number: 7880179Abstract: A process for producing electrical contact connections for a component integrated in a substrate material is provided, the substrate material having a first surface region, and at least one terminal contact being arranged at least partially in the first surface region for each component, which is distinguished in particular by application of a covering to the first surface region and production of at least one contact passage which, in the substrate material, runs transversely with respect to the first surface region, in which process, in order to form at least one contact location in a second surface region which is to be provided, at least one electrical contact connection from the contact location to at least one of the terminal contacts is produced via the respective contact passages.Type: GrantFiled: November 20, 2009Date of Patent: February 1, 2011Assignee: Wafer-Level Packaging Portfolio LLCInventors: Dipl.-Ing. Florian Bieck, Jürgen Leib
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Publication number: 20100327448Abstract: A packaging technique for electronic devices includes wafer fabrication of flexible contacts on the bottom surface of the substrate underneath the active circuit. Inherently reliable contacts suitable for a variety of devices can be formed via a simple fabrication process with good wafer packing density. For one embodiment, a trench is formed from the back of the substrate, exposing an upper conductive layer on the top surface. A standoff is formed on the bottom surface of the substrate. A lower conductive layer is formed that runs from and electrically connects with the exposed portion of the upper conductive layer onto the substrate standoff. The standoff is removed, releasing the formed conductors, resulting in a flexible contact.Type: ApplicationFiled: September 2, 2010Publication date: December 30, 2010Applicant: Wafer-Level Packaging Portfolio LLCInventor: Phil P. Marcoux
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Patent number: 7858512Abstract: A packaging technique for electronic devices includes wafer fabrication of flexible contacts on the bottom surface of the substrate underneath the active circuit. Inherently reliable contacts suitable for a variety of devices can be formed via a simple fabrication process with good wafer packing density. For one embodiment, a trench is formed from the back of the substrate, exposing an upper conductive layer on the top surface. A standoff is formed on the bottom surface of the substrate. A lower conductive layer is formed that runs from and electrically connects with the exposed portion of the upper conductive layer onto the substrate standoff. The standoff is removed, releasing the formed conductors, resulting in a flexible contact.Type: GrantFiled: June 26, 2008Date of Patent: December 28, 2010Assignee: Wafer-Level Packaging Portfolio LLCInventor: Phil P. Marcoux
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Publication number: 20100270668Abstract: A chip package transmitting slow speed signals via edge connectors and high speed signals by means of through-silicon-vias. The edge connectors are formed in recesses formed in the sidewalls of the package.Type: ApplicationFiled: April 28, 2009Publication date: October 28, 2010Applicant: WAFER-LEVEL PACKAGING PORTFOLIO LLCInventor: Phil P. Marcoux